1/8
PRELIMINARY DATA
June 2003
STD7NS20
STD7NS20-1
N-CHANNEL 200V - 0.35Ω - 7A DPAK / IPAK
MESH OVERLAY™ MOSFET
■ TYPICAL R
DS
(on) = 0.35 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ VERY LOW INTRINSIC CAPACITANCES
■ ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performance. The new patented STrip layout cou-
pled with the Company’s proprietary edge termina-
tion structure, makes it suitable in coverters for
lighting applications.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLIES (SMPS)
■ DC-DC CONVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
(•)Pulse width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STD7NS20
STD7NS20-1
200 V
200 V
< 0.40 Ω
< 0.40 Ω
7A
7A
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (V
GS
=0)
200 V
V
DGR
Drain-gate Voltage (R
GS
=20kΩ)
200 V
V
GS
Gate- source Voltage ± 20 V
I
D
Drain Current (continuos) at T
C
= 25°C
7A
I
D
Drain Current (continuos) at T
C
= 100°C
4.4 A
I
DM
( )
Drain Current (pulsed) 28 A
P
TOT
Total Dissipation at T
C
= 25°C
45 W
Derating Factor 0.37 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns
T
stg
Storage Temperature –65 to 150 °C
T
j
Max. Operating Junction Temperature 150 °C
(1) I
SD
≤ 7A, di/dt≤300 A/µs, V
DD
≤ V
(BR)DSS
,Tj≤T
jMAX
INTERNAL SCHEMATIC DIAGRAM
1
3
TO-252
DPAK
3
2
1
IPAK
TO-251
