OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

5V41067APGG8

P1-P3P4-P6P7-P9P10-P12P13-P13
DATASHEET
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER IDT5V41067A
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1
IDT5V41067A REV F 112211
Description
The IDT5V41067A is a 2:4 differential clock mux for PCI
Express applications. It has very low additive jitter making it
suitable for use in PCIe Gen2 and Gen3 systems. The
IDT5V41067A selects between 1 of 2 differential HCSL
inputs to fanout to 4 differential HCSL output pairs. The
outputs can also be terminated to LVDS.
Recommended Applications
• Clock muxing in PCIe Gen2 and Gen3 applications
Output Features
• 4 – 0.7V current mode differential HCSL output pairs
Features/Benefits
• Low additive jitter; suitable for use in PCIe Gen2 and
Gen3 systems
• 20-pin TSSOP package; small board footprint
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
• OE control pin; greater system power management
• Industrial temperature range available; supports
demanding embedded applications
Key Specifications
• Additive cycle-to-cycle jitter <5 ps
• Additive phase jitter (PCIe Gen2/3) <0.2ps
• Operating frequency up to 200MHz
Block Diagram
VDD
CLKA
CLKA
Rr (IREF)
CLKB
CLKB
CLKC
CLKC
CLKD
CLKD
SEL GND
IN1
IN1
IN2
IN2
MUX
2 to 1
OE
2
2
PD
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2
IDT5V41067A REV F 112211
Pin Assignment Select Table
Pin Descriptions
^SEL 1 20 DIF_0
VDDIN 2 19 DIF_0#
DIF_IN1 3 18 DIF_1
DIF_IN1# 4 17 DIF_1#
^PD# 5 16 GND
DIF_IN2 6 15 VDD
DIF_IN2# 7 14 DIF_2
^OE 8 13 DIF_2#
GND 9 12 DIF_3
IREF
10 11 DIF_3#
20-pin (1 73mil) TSSOP
5V41067
Note :
Pins preceeded by '*^ have internal
120K ohm pull up resistors
SEL Outputs
0DIF_IN2
1DIF_IN1
PIN # PIN NAME PIN TYPE DESCRIPTION
1
^
SE
L
IN Selects between one of two i n
p
uts. This
p
in has internal
p
ull u
p
resis tor.
2 VDDIN PWR Power
p
in for the In
p
uts, nominal 3.3 V
3 DIF_IN1 IN 0.7 V Differential TRUE in
p
ut
4 DIF_IN1# IN 0.7 V Differential Complementary Input
5^PD# IN
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
6 DIF_IN2 IN 0.7 V Differential TRUE in
p
ut
7 DIF_IN2# IN 0.7 V Differential Com
lementar
In
ut
8^OE IN
Active high input for enabling outputs. This pin has an internal pull up resistor.
0 = disable outputs, 1= enable outputs
9 GND PWR Ground pin.
10 IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
11 DIF_3# OUT 0.7V differential Com
p
lementar
y
clock out
p
ut
12 DIF_3 OUT 0.7V differential true clock output
13 DIF_2# OUT 0.7V differential Complementary clock output
14 DIF_2 OUT 0.7V differential true clock output
15 VDD PWR Power su
pp
l
y
, nominal 3.3V
16 GND PWR Ground
p
in.
17 DIF_1# OUT 0.7V differential Com
p
lementar
y
clock out
p
ut
18 DIF_1 OUT 0.7V differential true clock output
19 DIF_0# OUT 0.7V differential Complementary clock output
20 DIF_0 OUT 0.7V differential true clock output
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER 3
IDT5V41067A REV F 112211
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5V41067A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41067A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41067A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the Layout Guidelines section.
The IDT5V41067A can also be terminated to LVDS
compatible voltage levels. See the Layout Guidelines
section.
P1-P3P4-P6P7-P9P10-P12P13-P13

5V41067APGG8

Mfr. #:
Buy 5V41067APGG8
Manufacturer:
IDT
Description:
Clock Drivers & Distribution PCIe Gen2/3 2:4 DIFF CLOCK MUX/BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet