1. General description
The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by
the output enable inputs (nOE
). A HIGH on nOE causes the outputs to assume a high
impedance OFF-state. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
The 74HC125: CMOS levels
The 74HCT125: TTL levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
74HC125; 74HCT125
Quad buffer/line driver; 3-state
Rev. 5 — 19 January 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC125N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT125N
74HC125D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT125D
74HC125DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT125DB
74HC125PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74HCT125PW
74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 19 January 2015 2 of 17
NXP Semiconductors
74HC125; 74HCT125
Quad buffer/line driver; 3-state
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)
PQD
$ <
2(
$ <
2(
$ <

2(
$ <



2(
PQD
(1




PQD
Q2(
Q$
Q<
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
+&
+&7
2
(
9
&&
$
2(
<
$
2
(
<
$
2(
<
$
*1
'
<





DDD
74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 19 January 2015 3 of 17
NXP Semiconductors
74HC125; 74HCT125
Quad buffer/line driver; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: P
tot
derates linearly with 12 mW/K above 70 C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
Table 2. Pin description
Symbol Pin Description
1OE
, 2OE, 3OE, 4OE 1, 4, 10, 13 output enable input (active LOW)
1A, 2A, 3A, 4A 2, 5, 9, 12 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Control Input Output
nOE nA nY
LLL
HH
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V) - 35 mA
I
CC
supply current - +70 mA
I
GND
ground current - 70 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation
[2]
DIP14 package - 750 mW
SO14 and (T)SSOP14
packages
- 500 mW

74HC125N,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Buffers & Line Drivers QUAD BUFF/DRVR 3ST
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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