AD9281ARSZRL Datasheet AD9281ARSZ, AD7895ARZ-3, AD9281ARS | P10-P12

AD9281

–9–

The AD9281 can accommodate a variety of input spans be-

tween 1 V and 2 V. For spans of less than 1 V, expect a propor-

tionate degradation in SNR. Use of a 2 V span will provide the

best noise performance. 1 V spans will provide lower distortion

when using a 3 V analog supply. Users wishing to run with larger

full-scales are encouraged to use a 5 V analog supply (AVDD).

Single-Ended Inputs: For single-ended input signals, the

signal is applied to one input pin and the other input pin is tied

to a midscale voltage. This midscale voltage defines the center

of the full-scale span for the input signal.

EXAMPLE: For a single-ended input range from 0 V to 1 V

applied to IINA, we would configure the converter for a 1 V

reference (see Figure 17) and apply 0.5 V to IINB.

I OR QREFT

I OR QREFB

IINA

IINB

VREF

REF SENSE

0.1mF

10mF

0.1mF

AD9281

0.1mF

10mF

MIDSCALE

VOLTAGE

= 0.5V (1V)

INPUT

5kV 5kV

Figure 17. Example Configuration for 0 V–1 V Single-

Ended Input Signal

Note that since the inputs are high impedance, this reference

level can easily be generated with an external resistive divider

with large resistance values (to minimize power dissipation). A

decoupling capacitor is recommended on this input to minimize

the high frequency noise-coupling onto this pin. Decoupling

should occur close to the ADC.

Differential Inputs

Use of differential input signals can provide greater flexibility in

input ranges and bias points, as well as offering improvements in

distortion performance, particularly for high frequency input

signals. Users with differential input signals will probably want

to take advantage of the differential input structure of the AD9281.

Performance is still very good for single-ended inputs. Convert-

ing a single-ended input to a differential signal for application to

the converter is probably only worth considering for very high

frequency input signals.

AC-Coupled Inputs

If the signal of interest has no dc component, ac coupling can be

easily used to define an optimum bias point. Figure 18 illustrates

one recommended configuration. The voltage chosen for the dc

bias point (in this case the 1 V reference) is applied to both

IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA

is coupled to the input signal through Capacitor C1, while IINB is

decoupled to ground through Capacitor C2.

0.1mF

10mF

0.1mF

ANALOG

INPUT

1.0mF 0.1mF

1kV

1.5V

0.5V

I OR QREFT

I OR QREFB

IINA

IINB

VREF

AD9281

REFSENSE

Figure 18. Example Configuration for 0.5 V–1.5 V ac

Coupled Single-Ended Inputs

Transformer Coupled Inputs

Another option for input ac coupling is to use a transformer.

This not only provides dc rejection, but also allows truly differ-

ential drive of the AD9281’s analog inputs, which will provide

the optimal distortion performance. Figure 19 shows a recom-

mended transformer input drive configuration. Resistors R1 and

R2 define the termination impedance of the transformer cou-

pling. The center tap of the transformer secondary is tied to the

common-mode voltage, establishing the dc bias point for the

analog inputs.

0.1mF10mF

0.1mF

COMMON

MODE

VOLTAGE

0.1mF

10mF

I OR QREFT

I OR QREFB

IINA

IINB

AD9281

QINB

QINA

REFSENSE

VREF

Figure 19. Example Configuration for Transformer

Coupled Inputs

Crosstalk: The internal layout of the AD9281, as well as its

pinout, was configured to minimize the crosstalk between the

two input signals. Users wishing to minimize high frequency

crosstalk should take care to provide the best possible decoupling

for input pins (see Figure 20). R and C values will make a pole

dependant on antialiasing requirements. Decoupling is also

required on reference pins and power supplies (see Figure 21).

QINA

QINB

IINA

IINB

AD9281

Figure 20. Input Loading

DVDD

I OR QREFT

I OR QREFB

AVDD

0.1mF

10mF

0.1mF10mF

AD9281

0.1mF

0.1mF10mF

V ANALOG V DIGITAL

Figure 21. Reference and Power Supply Decoupling

REV. F

AD9281

–10–

REFERENCE AND REFERENCE BUFFER

The reference and buffer circuitry on the AD9281 is configured

for maximum convenience and flexibility. An illustration of the

equivalent reference circuit is show in Figure 26. The user can

select from five different reference modes through appropriate

pin-strapping (see Table I below). These pin strapping options

cause the internal circuitry to reconfigure itself for the appropri-

ate operating mode.

Table I. Table of Modes

Mode Input Span REFSENSE Pin Figure

1 V 1 V VREF 22

2 V 2 V AGND 23

Programmable 1 + (R1/R2) See Figure 24

External = External Ref AVDD 25

1 V Mode (Figure 22)—provides a 1 V reference and 1 V input

full scale. Recommended for applications wishing to optimize

high frequency performance, or any circuit on a supply voltage

of less than 4 V. The part is placed in this mode by shorting the

REFSENSE pin to the VREF pin.

I OR QREFT

I OR QREFB

IINA

IINB

VREF

0.1mF10mF

0.1mF

AD9281

0.1mF

10mF

QINB

QINA

5kV

REFSENSE

Figure 22. 0 V to 1 V Input

2 V Mode (Figure 23)—provides a 2 V reference and 2 V input

full scale. Recommended for noise sensitive applications on 5 V

supplies. The part is placed in 2 V reference mode by ground-

ing (shorting to AVSS) the REFSENSE pin.

I OR QREFT

I OR QREFB

IINA

IINB

VREF

0.1mF10mF

0.1mF

AD9281

0.1mF

10mF

QINB

QINA

5kV

REFSENSE

Figure 23. 0 V to 2 V Input

Externally Set Voltage Mode (Figure 24)—this mode uses

the on-chip reference, but scales the exact reference level though

the use of an external resistor divider network. VREF is wired to

the top of the network, with the REFSENSE wired to the tap

point in the resistor divider. The reference level (and input full

scale) will be equal to 1 V × (R1 + R2)/R1. This method can be

used for voltage levels from 0.7 V to 2.5 V.

I OR QREFT

I OR QREFB

VREF

0.1mF10mF

0.1mF

AD9281

REFSENSE

–

AVSS

0.1mF

1mF

VREF = 1 +

–

Figure 24. Programmable Reference

External Reference Mode (Figure 25)—in this mode, the on-

chip reference is disabled, and an external reference applied to

the VREF pin. This mode is achieved by tying the REFSENSE

pin to AVDD.

EXT

REFERENCE

AVDD

I OR QREFT

I OR QREFB

IINA

IINB

VREF

0.1mF10mF

0.1mF

AD9281

0.1mF

10mF

QINB

QINA

5kV

REFSENSE

Figure 25. External Reference

Reference Buffer—The reference buffer structure takes the

voltage on the VREF pin and level-shifts and buffers it for use

by various sub-blocks within the two A/D converters. The two

converters share the same reference buffer amplifier to maintain

the best possible gain match between the two converters. In the

interests of minimizing high frequency crosstalk, the buffered

references for the two converters are separately decoupled on

the IREFB, IREFT, QREFB and QREFT pins, as illustrated in

Figure 26.

REV. F

AD9281

–11–

QREFT

QREFB

IREFT

0.1mF10mF

0.1mF

AD9281

REFSENSE

AVSS

0.1mF10mF

IREFB

VREF

0.1mF

10kV

ADC

CORE

INTERNAL

CONTROL

LOGIC

0.1mF1.0mF

Figure 26. Reference Buffer Equivalent Circuit and

External Decoupling Recommendation

For best results in both noise suppression and robustness

against crosstalk, the 4-capacitor buffer decoupling arrangement

shown in Figure 26 is recommended. This decoupling should

–3

–0.5

THD – dB

–13

–23

–33

–43

–53

–63

–73

0 0.5 1 1.5

CML – V

a. Differential Input, 3 V Supplies

–35

–0.5

THD – dB

–40

–45

–50

–55

–60

–65

–70

0 0.5 1 1.5

CML – V

2 2.5

b. Differential Input, 5 V Supplies

Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz)

–15

–0.5

THD – dB

–25

–35

–45

–55

–65

0 0.5 1 1.5

CML – V

c. Single-Ended Input, 3 V Supplies

–15

–0.5

THD – dB

–25

–35

–45

–55

–65

0 0.5 1 1.5

CML – V

2 2.5

d. Single-Ended Input, 5 V Supplies

feature chip capacitors located close to the converter IC. The

capacitors are connected to either IREFT/IREFB or QREFT/

QREFB. A connection to both sides is not required.

COMMON-MODE PERFORMANCE

Attention to the common-mode point of the analog input volt-

age can improve the performance of the AD9281. Figure 27

illustrates THD as a function of common-mode voltage (center

point of the analog input span) and power supply.

Inspection of the curves will yield the following conclusions:

1. An AD9281 running with AVDD = 5 V is the easiest to

drive.

2. Differential inputs are the most insensitive to common-mode

voltage.

3. An AD9281 powered by AVDD = 3 V and a single ended

input, should have a 1 V span with a common-mode voltage

of 0.75 V.

REV. F

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AD9281ARSZRL

Mfr. #:

Buy AD9281ARSZRL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Dual CH 8-Bit Resolution CMOS

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD9281ARSZRL

AD9281ARSZRL

Products related to this Datasheet