LTC3561A
16
3561afa
For more information www.linear.com/LTC3561A
APPLICATIONS INFORMATION
The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, C
IN
is typically
10µF. In noisy environments, decoupling SV
IN
from PV
IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
For the feedback resistors, choose R1 = 200k, R2 can be
calculated from:
R
V
R
V
V
k
OUT
2
08
11
18
08
1 200=
=
.
–•
.
.
–• == 250k
Choose a standard value of 249k for R2.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the L
TC3561A is with a 16.9kΩ and 680pF filter
.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3561A. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 5)
and power GND (Pin 4) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to PGND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line terminated
near SGND. The feedback signal V
FB
should be routed away
from noisy components and traces, such as the SW line
(Pin 3), and its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C
IN
, the compensation capacitor C
C
and
C
ITH
and all the resistors R1, R2, R
T
, and R
C
should be
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, route all
small-signal components back to the SGND pin. All SGND
and PGND pins must be connected together through a
thick copper trace or ground plane.
6. Flood all unused areas on all layers with copper. Flood
-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
the exposed pad for best results.
Figure 6. LTC3561A Layout Diagram (See Board Layout Checklist)
PV
IN
LTC3561A
PGND
SW
SV
IN
SGNDV
FB
I
TH
SHDN/R
T
L1
V
IN
V
OUT
R
T
R
C
R1R2
3561A F06
C
C
C
ITH
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
C
OUT
C4
LTC3561A
17
3561afa
For more information www.linear.com/LTC3561A
General Purpose Buck Regulator Using Ceramic Capacitors
Efficiency vs Output Current
TYPICAL APPLICATION
SV
IN
LTC3561A
SW
PV
IN
V
FB
I
TH
SHDN/R
T
SGND
L1
2.2µH
V
IN
2.5V TO
5.5V
V
OUT
1.2V/1.5V/1.8V
AT 1A
R4
549k
R1A
200k
3561A TA02a
C3
680pF
R3
16.9k
C4 22pF
R2 249k
C2
22µF
SGND
R1B
287k
R1C
499k
PGND
C1
22µF
PGND
PGNDSGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
GND
1.8V 1.5V 1.2V
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3561A TA02b
0
10
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
V
OUT
= 1.2V
V
IN
= 3.6V
V
OUT
= 1.2V
I
LOAD
= 20mA TO 1A
V
OUT
100mV/DIV
AC COUPLED
I
L
1A/DIV
3561A TA02c
40µs/DIV
I
LOAD
1A/DIV
V
IN
= 3.6V
V
OUT
= 1.2V
I
LOAD
= 200mA TO 1A
V
OUT
100mV/DIV
AC COUPLED
I
L
1A/DIV
3561A TA02d
40µs/DIV
I
LOAD
1A/DIV
LTC3561A
18
3561afa
For more information www.linear.com/LTC3561A
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ±0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3561AEDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1A, 4MHz, Sync Buck DC/DC Conv
Lifecycle:
New from this manufacturer.
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