25LCXXXA
DS22136B-page 14 Preliminary © 2009 Microchip Technology Inc.
4.0 DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
5.0 POWER-ON STATE
The 25LCXXXA powers on in the following state:
• The device is in low-power Standby mode
(CS= 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS
is required to
enter active state
TABLE 5-1: WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
WEL
(SR bit 1)
Protected Blocks Unprotected Blocks STATUS Register
0 (low) x
Protected Protected Protected
1 (high) 0
Protected Protected Protected
1 (high) 1
Protected Writable Writable
x = don’t care
