7
© 2007 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC2608B
Applications Information (Cont.)
The control model of SC2608B is depicted in Fig. 4.
This model can also be used to generate loop gain Bode
plots. The bandgap reference is 0.8V and trimmed to
+/-1% accuracy. The desired output voltage can be
achieved by setting the resistive divider network, R1 and
R2. The error amplifier is transconductance type with fixed
gain of:
The compensation network includes a resistor and a ca-
pacitor in series, which terminates the output of the
error amplifier to the ground.
The task here is to properly choose the compensation
network for a nicely shaped loop-gain Bode plot. The
following design procedures are recommended to accom-
plish the goal:
(1) Calculate the corner frequency of the output filter:
(2) Calculate the ESR zero frequency of the output filter
capacitor:
(3) Check that the ESR zero frequency is not too high.
If this condition is not met, the compensation structure
may not provide loop stability. The solution is to add
some electrolytic capacitors to the output capacitor bank
to correct the output filter corner frequency and the ESR
zero frequency. In some cases, the filter inductance may
also need to be adjusted to shift the filter corner fre-
quency. It is not recommended to use only high frequency
multi-layer ceramic capacitors for output filter.
(4) Choose the loop gain cross over frequency (0 dB fre-
quency). It is recommended that the crossover frequency
is always less than one fifth of the switching frequency :
If the transient specification is not stringent, it is better
to choose a crossover frequency that is less than one
tenth of the switching frequency for good noise immu-
nity. The resistor in the compensation network can then
be calculated as:
when
Fig. 4. SC2608B small signal model.
VIN
C
G_PWM
RcR
E/A
VBG
0.8V
Ro
L
R1
Ci
R2Co
() ()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
+
••
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
•••=
o
c
o
o
oc
oc
c
o
bg
inpwmm
R
R
LCs
R
L
CRs
CsR
sH
V
V
VGGsT
11
1
2
()
i
c
sC
sC
R
sH
+
+
=
1
1
1
o
o
LC
F
π
2
1
=
oc
esr
CR
F
π
2
1
=
5
SW
esr
F
F <
SWOVERX
FF •=
5
1
_
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
•
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
•
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
•
••
=
bg
o
esr
OVERX
o
esr
minpwm
V
V
F
F
F
F
GVG
R
_
2
1
F
o
F
esr
<
F
sw
5
<
V
A
G
m
007.0
=
The total control loop-gain can then be derived as
follows:
where the ramp amplitude is fixed at 1 volts.
ramp
pwm
V
G
1
=
Compensation Network DesignCompensation Network Design
Compensation Network DesignCompensation Network Design
Compensation Network Design
A note to the user is needed: The device cannot restart
until both COMP and SENSE are low, to prevent start up
into a charged output. In the event of an overcurrent
condition, the output is quickly discharged by the load,
therefore bringing SENSE below the 300mV threshold. If
the COMP pin is pulled low by an external device (such as
an open-drain logic gate used for system shutdown), and
SENSE is high(above 300mV) while COMP is low, then the
SC2608B turns on the low side FET to discharge the output
before changing to shutdown or soft-start mode. The low
side FET turns off when SENSE drops below 300mV and
the converter remains in the tri-state condition until COMP
is released. Although this shutdown technique can be used
successfully on the SC2608B, the system designer using
COMP for external shutdown will need to consider the load
on the low side FET when discharging the output capacitor
bank. For large capacitor bank, this peak current can be
quite large as it is limited only by the R
DS(ON)
of the low side
FET. Fortunately the duration of this event is quite short,
and has been shown in the lab to have no detrimental effect
on the performance of the external FETs.
Disabling the output by pulling down COMP/SS pin is only
recommended when the output capacitor bank is not too
large.
The PWM gain is inversion of the ramp amplitude, and
this gain is given by:
