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AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Device Operation
READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WEis
high, the data stored at the memory location determined by the address pins is asserted on the
outputs. The outputs are put in the high impedance state when either
CEorOE is high. This
dual-line control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE: A low pulse on the
WE or CE input with CE or WE low (respectively) and OE high
initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started
it will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
WC
, a read operation will effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be
written into the device during a single internal programming period. A page write operation is ini-
tiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127
additional bytes. Each successive byte must be written within 150s(t
BLC
) of the previous byte.
If the t
BLC
limit is exceeded the AT28C010 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the
page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes which
are specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle.
During a byte or page write cycle an attempted read of the last byte written will result in the com-
plement of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at
anytime during the write cycle.
TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determin-
ing the end of a write cycle. During the write operation, successive attempts to read data from
the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during
the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transi-
tions of the host system power supply. Atmel has incorporated both hardware and software fea-
tures that will protect the memory against inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the
AT28C010 in the following ways: (a) V
CC
sense - if V
CC
is below 3.8V (typical) the write function
is inhibited; (b) V
CC
power-on delay - once V
CC
has reached 3.8V the device will automatically
time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OElow,CE
high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has been
implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent
inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after t
WC
the entire AT28C010 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C010. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable SDP.
