ISL6405EEB Datasheet ISL6405EVAL1, ISL6405ERZ-T, ISLUSBI2CKIT1Z | P7-P9

Functional Description

The ISL6405 dual output voltage regulator makes an ideal

choice for advanced satellite set-top box and personal video

recorder applications. Both supply and control voltage

outputs for two low-noise blocks (LNBs) are available

simultaneously in any output configuration. The device

utilizes built-in DC/DC step-converters that, from a single

supply source ranging from 8V to 14V, generate the voltages

that enable the linear post-regulators to work with a

minimum of dissipated power. An undervoltage lockout

circuit disables the circuit when VCC drops below a fixed

threshold (7.5V typ).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone

of 22kHz in accordance with DiSEqC (EUTELSAT)

standards. No further adjustment is required. The 22kHz

oscillator can be controlled either by the I

C interface

(ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows

immediate DiSEqC data encoding separately for each LNB.

(Please see Note 1 at the end of this section.) All the

functions of this IC are controlled via the I

C bus by writing

to the system registers (SR1, SR2). The same registers

can be read back, and two bits will report the diagnostic

status. The internal oscillator operates the converters at ten

times the tone frequency. The device offers full I

compatible functionality, 3.3V or 5V, and up to 400kHz

operation.

If the Tone Enable (ENT1/2) bit is set LOW through I

C, then

the DSQIN1/2 terminal activates the internal tone signal,

modulating the dc output with a 0.3V, 22kHz, symmetrical

waveform. The presence of this signal usually gives the LNB

information about the band to be received.

Burst coding of the 22kHz tone can be accomplished due to

the fast response of the DSQIN1/2 input and rapid tone

response. This allows implementation of the DiSEqC

(EUTELSAT) protocols.

When the ENT1/2 bit is set HIGH, a continuous 22kHz tone

is generated regardless of the DSQIN1/2 pin logic status for

the corresponding regulator channel (LNB-A or LNB-B). The

ENT1/2 bit must be set LOW when the DSQIN1 and/or

DSQIN2 pin is used for DiSEqC encoding.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.25µF. In order to minimize the power

dissipation, the output voltage of the internal step-up

converter is adjusted to allow the linear regulator to work at

minimum dropout.

When the device is put in the shutdown mode (EN1,

EN2 = LOW), both PWM power blocks are disabled. (i.e.

when EN1 = 0, PWM1 is disabled, and when EN2 = 0,

PWM2 is disabled).

When the regulator blocks are active (EN1, EN2 = HIGH),

the output can be logic controlled to be 13V or 18V (typical)

by mean of the VSEL bit (Voltage Select) for remote

controlling of non-DiSEqC LNBs. Additionally, it is possible

to increment by 1V (typical) the selected voltage value to

compensate for the excess voltage drop along the coaxial

cable (LLC1/2 bit HIGH).

Output Timing

The programmed output voltage rise and fall times can be

set by an external capacitor. The output rise and fall times

will be approximately 3400 times the TCAP value. For the

recommended range of 0.47µF to 2.2µF, the rise and fall

time would be 1.6ms to 7.6ms. Using a 0.47µF capacitor

insures the PWM stays below its overcurrent threshold when

charging a 120µF VSW filter cap during the worst case 13V

to 19V transition. A typical value of 1.0µF is recommended.

Functional Pin Description

SYMBOL FUNCTION

SDA Bidirectional data from/to I

C bus.

SCL Clock from I

C bus.

VSW1, 2 Input of the linear post-regulator.

PGND1, 2 Dedicated ground for the output gate driver of

respective PWM.

CS1, 2 Current sense input; connect Rsc at this pin for

desired over current value for respective PWM.

SGND Small signal ground for the IC.

AGND Analog ground for the IC.

TCAP1, 2 Capacitor for setting rise and fall time of the output

of LNB A and LNB B respectively. Use this

capacitor value 1µF or higher.

BYPASS Bypass capacitor for internal 5V.

DSQIN1, 2 When HIGH enables internal 22kHz modulation for

LNB A and LNA B respectively, Use this pin for

tone enable function for LNB A and LNB B.

VCC Main power supply to the chip.

GATE1, 2 These are the device outputs of PWM A and

PWM B respectively. These high current driver

outputs are capable of driving the gate of a power

FET. These outputs are actively held low when

Vcc is below the UVLO threshold.

VO1, 2 Output voltage of LNB A and LNB B respectively.

ADDR Address pin to select two different addresses per

voltage level at this pin.

COMP1, 2 Error amp outputs used for compensation.

FB1, 2 Feedback pins for respective PWMs

CPVOUT,

CPSWIN,

CPSWOUT

Charge pump connections.

SEL18V1, 2 When connected HIGH, this pin will change the

output of the respective PWM to 18V. Only

available on the QFN package option.

ISL6405

This feature only affects the turn-on and programmed

voltage rise and fall times.

Current Limiting

The current limiting block has two thresholds that can be

selected by the ISEL bit of the SR and can work either

statically (simple current clamp) or dynamically. The lower

threshold is between 425mA and 530mA (ISEL = L), while

the higher threshold is between 775mA and 925mA

(ISEL = H). When the DCL (Dynamic Current Limiting) bit is

set to LOW, the over current protection circuit works

dynamically: as soon as an overload is detected, the output

is shutdown for a time t

OFF

, typically 900ms. Simultaneously

the OLF bit of the System Register is set to HIGH. After this

time has elapsed, the output is resumed for a time t

20ms. During t

, the device output will be current limited to

425mA or 775mA, depending on the ISEL bits. At the end of

, if the overload is still detected, the protection circuit will

cycle again through t

OFF

and t

. At the end of a full t

which no overload is detected, normal operation is resumed

and the OLF bit is reset to LOW. Typical t

+ t

OFF

time is

920ms as determined by an internal timer. This dynamic

operation can greatly reduce the power dissipation in a short

circuit condition, still ensuring excellent power-on start-up in

most conditions.

However, there could be some cases in which a highly

capacitive load on the output may cause a difficult start-up

when the dynamic protection is chosen. This can be solved

by initiating any power start-up in static mode (DCL = HIGH)

and then switching to the dynamic mode (DCL = LOW) after

a chosen amount of time. When in static mode, the OLF1/2

bit goes HIGH when the current clamp limit is reached and

returns LOW when the overload condition is cleared. The

OLF1/2 bit will be LOW at the end of initial power-on soft-start.

Thermal Protection

This IC is protected against overheating. When the junction

temperature exceeds 150°C (typical), the step-up converter

and the linear regulator are shut off and the OTF bit of the

SR is set HIGH. Normal operation is resumed and the OTF

bit is reset LOW when the junction is cooled down to 135°C

(typical).

In over temperature conditions, the OTF Flag goes HIGH

and the I

C data will be cleared. The user may need to

monitor the I

C enable bits and OTF flag continuously and

enable the chip, if I

C data is cleared. OTF conditions may

also make the OLF flags go HIGH, when high capacitive

loads are present or self-heating conditions occur at higher

loads.

External Output Voltage Selection

The output voltage can be selected by the I

C bus.

Additionally, the QFN package offers two pins (SEL18V1,

SEL18V2) for independent 13V/18V output voltage

selection. When using these pins, the I

C bits should be

initialized to 13V status.

C Bus Interface for ISL6405

(Refer to Philips I

C Specification, Rev. 2.1)

Data transmission from main microprocessor to the ISL6405

and vice versa takes place through the two wire I

C bus

interface, consisting of the two lines SDA and SCL. Both SDA

and SCL are bidirectional lines, connected to a positive supply

voltage via a pull up resistor. (Pull up resistors to positive supply

voltage must be externally connected). When the bus is free,

both lines are HIGH. The output stages of ISL6405 will have an

open drain/open collector in order to perform the wired-AND

function. Data on the I

C bus can be transferred up to 100Kbps

in the standard-mode or up to 400Kbps in the fast-mode. The

level of logic “0” and logic “1” is dependent of associated value

of V

as per electrical specification table. One clock pulse is

generated for each data bit transferred.

Data Validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW. Refer to Figure 1.

START and STOP Conditions

As shown in Figure 2, START condition is a HIGH to LOW

transition of the SDA line while SCL is HIGH.

The STOP condition is a LOW to HIGH transition on the SDA

line while SCL is HIGH. A STOP condition must be sent

before each START condition.

TABLE 1.

C BITS SEL18V (1, 2) O/P VOLTAGE

13V Low 13V

14V Low 14V

13V High 18V

14V High 19V

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

FIGURE 1. DATA VALIDITY

SDA

SCL

START

CONDITION

FIGURE 2. START AND STOP WAVEFORMS

STOP

CONDITION

ISL6405

Byte Format

Every byte put on the SDA line must be eight bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most significant

bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on

the SDA line during the acknowledge clock pulse (Figure 3).

The peripheral that acknowledges has to pull down (LOW)

the SDA line during the acknowledge clock pulse, so that the

SDA line is stable LOW during this clock pulse. (Of course,

set-up and hold times must also be taken into account.)

The peripheral which has been addressed has to generate

an acknowledge after the reception of each byte, otherwise

the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

The ISL6405 will not generate the acknowledge if the

POWER OK signal from the UVLO is LOW.

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the

microprocessor can use a simpler transmission; it waits one

clock without checking the slave acknowledging, and sends

the new data.

This approach, though, is less protected from error and

decreases the noise immunity.

ISL6405 Software Description

Interface Protocol

The interface protocol is comprised of the following, as

shown below in Table 2:

• A start condition (S)

• A chip address byte (MSB on left; the LSB bit determines

read (1) or write (0) transmission) (the assigned I

C slave

address for the ISL6405 is 0001 00XX)

• A sequence of data (1 byte + Acknowledge)

• A stop condition (P)

System Register Format

• R, W = Read and Write bit

• R = Read-only bit

All bits reset to 0 at Power-On

SDA

SCL

FIGURE 3. ACKNOWLEDGE ON THE I

C BUS

ACKNOWLEDGE

FROM SLAVE

MSB

START

TABLE 2. INTERFACE PROTOCOL

S0001000R/WACK Data (8 bits) ACKP

TABLE 3. SYSTEM REGISTER 1 (SR1)

R, W R, W R, W R, W R, W R, W R, W R

SR1 DCL ISEL1 ENT1 LLC1 VSEL1 EN1 OLF1

TABLE 4. SYSTEM REGISTER 2 (SR2)

R, W R, W R, W R, W R, W R, W R R

SR2 ISEL2 ENT2 LLC2 VSEL2 EN2 OTF OLF2

ISL6405

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ISL6405EEB

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ISL6405EEB

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