Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. D
06/21/2011
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IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-20 ns -25 ns -35 ns -45ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 20 — 25 — 35 — 45 — ns
tSCE CE to Write End 12 — 18 — 25 — 35 — ns
tAW Address Setup Time 12 — 15 — 25 — 35 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 12 — 18 — 30 — 35 — ns
tPWE1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — 35 — ns
tPWE2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — 35 — ns
tSD Data Setup to Write End 9 — 12 — 15 — 20 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 9 — 12 — 20 — 20 ns
tLZWE
(3)
WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
