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2014-01-0009 PT0485-1 02/11/14
6
PI6ULS5V9627A
4 Channel Level Translating
Fast-Mode Plus I
2
C-bus/SMbus Repeater
Figure 5: Test Circuit
Functional Description
The PI6ULS5V9627A enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 0.6 V without degradation of system
performance. The PI6ULS5V9627A contains two bidirectional open-drain buffers specifically designed to support up-
translation/down-translation between the low voltage (as low as 0.6 V) and a 2.5 V, 3.3 V or 5 V I
2
C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V
CC(B)
and/or V
CC(A)
= 0 V).
The PI6ULS5V9627A includes a power-up circuit that keeps the output drivers turned off until V
CC(B)
is above 2.2 V and until
after the internal reference circuits have settled at about 400 μs, and the V
CC(A)
is above 0.6 V. V
CC(B)
and V
CC(A)
can be applied in
any sequence at power-up.
The PCA9627A includes a VCC(A) over-voltage disable that turns the channel off if 0.4VCC(A) + 0.8 V >
VCC(B). The PCA9627A logic and all I/Os are powered by the VCC(B) pins.
The B-side drivers operate from 2.2V to 5.5V. The output low level of port B internal buffer is approximately 0.55 V, while
the input voltage must be 90mV lower (0.45V) or even more lower. The nearly 0.5V low signal is called a buffered low. When the
B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from
occurring when the input low condition is released. This type of design on B port prevents it from being used in series with
another PI6ULS5V9627A (B side) or similar devices, because they don’t recognize buffer low signals as a valid low .
The A-side drivers operate from 0.6V to 5.5V. The output low level of port A internal buffer is nearly 0V, while the input low
level is set at 0.35V
CC(A)
to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is
as low as 0.6 V. Port A of two or more PI6ULS5V9627As can be connected together to allow a star topography with port A on the
common bus. And port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple
PI6ULS5V9627As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays
to consider.
After power-up and with the EN HIGH, a LOW level on port A (below 0.3V
CC(A)
) turns the corresponding port B driver (either
SDA or SCL) on and drives port B down to about 0.55V. When port A rises above 0.3V
CC(A)
, the port B pull-down driver is turned
off and the external pull-up resistor pulls the pin HIGH. When port B falls first and goes below 0.4 V, the port A driver is turned
on and port A pulls down to about 0 V. The port A pull-down is not enabled unless the port B voltage goes below 0.4V. If the port
B low voltage goes below 0.4 V, the port B pull-down driver is enabled and port B will only be able to rise to 0.55 V until port A
rises above 0.3V
CC(A)
, then port B will continue to rise being pulled up by the external pull-up resistor. The V
CC(A)
is only used to
provide the 0.35V
CC(A)
reference to the port A input comparators and for the power good detect circuit. The PI6ULS5V9627A
logic and all I/Os are powered by the V
CC(B)
pin.
The EN pin is active HIGH with thresholds referenced to V
CC(B)
and an internal pull-up to V
CC(B)
that maintains the device
active unless the user selects to disable the repeater to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
2
C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I
2
C-bus parts being enabled. The enable does not switch the internal
reference circuits so the 400μs delay is only seen when V
CC(B)
comes up. The enable pin should only change state when the global
bus and the repeater port are in an idle state to prevent system failures.
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus
(standard open-collector configuration of the I
2
C-bus). The size of these pull-up resistors depends on the system, but each side of
the repeater must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode and Fast-mode Plus I
2
C-bus
devices in addition to SMBus devices. Standard mode and Fast-mode I
2
C-bus devices only specify 3mA output drive; this limits
the termination current to 3mA in a generic I
2
C-bus system where Standard-mode devices, Fast-mode devices and multiple
masters are possible. When only Fast-mode Plus devices are used with 30mA at 5V drive strength, then lower value pull-up
resistors can be used. The B-side RC should not be less than 67.5ns because shorter RCs increase the turnaround bounce when the
B-side transitions from being externally driven to pulled down by its offset buffer.
R
L
= load resistor; 1.35 kΩ on port B
C
L
= load capacitance includes jig and probe capacitance; 50 pF
R
T
= termination resistance should be equal to Z
0
of pulse generators
