13
LTC3716
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low
current operation must also be considered. The PolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current I
L
per individual section, N,
decreases with higher inductance or frequency and
increases with higher V
IN
or V
OUT
:
I
V
fL
V
V
L
OUT OUT
IN
=−
1
where f is the individual output stage operating frequency.
In a 2-phase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for 1- and 2-phase configurations. The output
ripple current is plotted for a fixed output voltage as the
duty factor is varied between 10% and 90% on the x-axis.
The output ripple current is normalized against the induc-
tor ripple current at zero duty factor. The graph can be
used in place of tedious calculations, simplifying the
design process.
Accepting larger values of I
L
allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
I
L
= 0.4(I
OUT
)/2, where I
OUT
is the total load current.
Remember, the maximum I
L
occurs at the maximum
input voltage. The individual inductor ripple currents are
determined by the inductor, input and output voltages.
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ
®
cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductor type selected. As
inductance increases, core losses go down. Unfortu-
nately, increased inductance requires more turns of wire
and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple.
Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi-
cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
output stage with the LTC3716: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage. This voltage is typically 5V during start-up
APPLICATIO S I FOR ATIO
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Kool Mµ is a registered trademark of Magnetics, Inc.
Figure 3. Normalized Output Ripple Current
vs Duty Factor [I
RMS
0.3 (I
O(P–P)
)]
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3716 F03
2-PHASE
1-PHASE
I
O(P-P)
V
O
/fL
14
LTC3716
(see EXTV
CC
Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V
IN
< 5V); then, sublogic-level threshold MOSFETs
(V
GS(TH)
< 1V) should be used. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC3716 is operating in continuous mode the duty factors
for the top and bottom MOSFETs of each output stage are
given by:
Main SwitchDuty Cycle
V
V
OUT
IN
=
Synchronous SwitchDuty Cycle
VV
V
IN OUT
IN
=
The MOSFET power dissipations at maximum output
current are given by:
P
V
V
I
R
kV
I
Cf
MAIN
OUT
IN
MAX
DS ON
IN
MAX
RSS
=
+
()
+
()
()()
2
1
2
2
2
δ
()
P
VV
V
I
R
SYNC
IN OUT
IN
MAX
DS ON
=
+
()
()
2
1
2
δ
where δ is the temperature dependency of R
DS(ON)
and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
RSS
actual provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
The Schottky diodes, D1 and D2 shown in Figure 1
conduct during the dead-time between the conduction of
the two large power MOSFETs. This helps prevent the
body diode of the bottom MOSFET from turning on,
storing charge during the dead-time, and requiring a
reverse recovery period which would reduce efficiency. A
1A to 3A Schottky (depending on output current) diode is
generally a good compromise for both regions of opera-
tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the input voltage is twice the
output voltage.
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
V
V
k
OUT
IN
=
21
4
where k = 1, 2
These worst-case conditions are commonly used for
design because even significant deviations do not offer
APPLICATIO S I FOR ATIO
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15
LTC3716
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.
The output ripple varies with input voltage since I
L
is a
function of input voltage. The output ripple will be less than
50mV at max V
IN
with I
L
= 0.4I
OUT(MAX)
/2 assuming:
C
OUT
required ESR < 4(R
SENSE
) and
C
OUT
> 1/(16f)(R
SENSE
)
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally com-
pensate the switching regulator loop using the I
TH
pin(OPTI-LOOP compensation) allows a much wider se-
lection of output capacitor types. OPTI-LOOP compensa-
tion effectively removes constraints on output capacitor
ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo and the Panasonic
SP surface mount types have the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON type capacitors is recommended to reduce
the inductance effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur-
face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, POSCAPs, Panasonic SP caps, Nichicon
PL series and Sprague 595D series. Consult the manufac-
turer for other specific recommendations. A combination
of capacitors will often result in maximizing performance
and minimizing overall cost and size.
APPLICATIO S I FOR ATIO
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Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3716 F04
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
2-PHASE
1-PHASE
It is important to note that the efficiency loss is propor-
tional to the input RMS current
squared
and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the
reduction of the input ripple current in a 2-phase system.
The required amount of input capacitance is further
reduced by the factor, 2, due to the effective increase in
the frequency of the current pulses.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (V
OUT
) is determined by:
∆∆V I ESR
fC
OUT RIPPLE
OUT
≈+
1
16
Where f = operating frequency of each stage, C
OUT
=
output capacitance and I
RIPPLE
= combined inductor
ripple currents.

LTC3716EG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Phase Step Down Converter
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