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ADG1234YCPZ-REEL7
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
Data Sheet
ADG1233/ADG1234
Rev.
D
| P
age
13
of
17
FREQ
UENCY
(Hz)
ON RESPONSE (dB)
0
–5
–10
–15
–20
–25
10k
100k
1M
10M
100M
10G
1G
05743-013
V
DD
= +15V
V
SS
= –15V
T
A
= 25°
C
Figure
19
.
On Respo
nse vs. Frequen
cy
FREQ
UENCY
(Hz)
THD + N (
%)
10
1
0.10
0.01
10
100
1k
10k
100k
05743-037
LO
AD =
10kΩ
T
A
= 25°
C
V
DD
= +5V, V
SS
= –5V,
V
S
= +3.
5V rms
V
DD
= +15V,
V
SS
= –15V,
V
S
= +5V rms
Figure
20
.
THD + N vs. Freq
uency
V
BIAS
(V)
CAPACIT
ANCE (
pF
)
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0
–15
–10
–5
0
15
10
5
05743-010
SOURCE
/DRAI
N ON
DRAIN O
FF
SOURCE
OF
F
V
DD
= +15V
V
SS
= –15V
T
A
= 25°
C
Figure
21
. Capacita
nce vs. Source
Voltage fo
r Dual Supply
V
BIAS
(V)
CAPACIT
ANCE (
pF
)
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0
0
2
4
6
8
10
12
05743-009
SOURCE
/DRAI
N ON
DRAIN O
FF
SOURCE
OF
F
V
DD
= 12V
V
SS
= 0V
T
A
= 25°
C
Figure
22
. Capacita
nce vs. Source
Voltage fo
r Single Supply
V
BIAS
(V)
CAPACIT
ANCE (
pF
)
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0
–5
–4
–2
–3
–1
0
1
2
3
4
5
05743-007
SOURCE
/DRAI
N ON
DRAIN O
FF
SOURCE
OF
F
V
DD
= +5V
V
SS
= –5V
T
A
= 25°
C
Figure
23
. Capacita
nce vs. Source
Voltage fo
r Dual Su
pply
ADG1233/ADG1234
Data Sheet
Rev. D | Page 14 of 17
TEST CIRCUITS
I
DS
SD
V
S
05743-020
V
Figure 24. On Resistance
SD
V
S
A
A
V
D
I
S
(OFF)
I
D
(OFF)
05743-021
Figure 25. Off Leak
age
SD
A
V
D
I
D
(ON)
NC
NC = NO CO
NNECT
05743-022
Figure 26. On Leakage
05743-023
INx
V
OU
T
D
SxA
V
DD
V
SS
V
DD
V
SS
GN
D
C
L
35pF
SxB
V
IN
V
S
0.1µF
0.1µ
F
R
L
300
Ω
50%
50%
90%
50%
50%
90%
t
ON
t
OFF
V
IN
V
OU
T
V
IN
Figure 27. Swit
ching Timing
05743-024
IN
x
V
OU
T
D
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µ
F
0.1µ
F
R
L
300
Ω
80%
t
BBM
t
BBM
V
OUT
V
IN
Figure 28. Break-Before-M
ake Delay
Data Sheet
ADG1233/ADG1234
Rev. D | Page 15 of 17
OUT
PUT
3V
0V
0V
V
O
ENABLE
DRIVE
(V
IN
)
05743-025
EN
IN3
IN2
IN1
S1B
D1
V
DD
V
SS
V
DD
V
SS
GND
ADG1233
R
L
300
Ω
C
L
35pF
V
S
50%
0.9V
O
0.9V
O
t
ON
(EN)
50%
V
O
S1A
V
IN
0.1µ
F
0.
1µ
F
50
Ω
t
OFF
(EN)
Figure 29. Enable De
lay, t
ON
(
EN
), t
OFF
(
EN
)
V
IN
(NOR
MALLY
CLO
SED SW
IT
CH)
V
OU
T
V
IN
(NOR
MALLY
OPEN SWITCH)
OFF
∆
V
OUT
ON
Q
INJ
= C
L
×
∆
V
OU
T
05743-026
INx
V
OUT
D
SxA
V
DD
V
SS
V
DD
V
SS
GN
D
C
L
1nF
NC
SxB
V
IN
V
S
0.1µ
F
0.1µ
F
Figure 30. Charge I
njection
V
OUT
50
Ω
NETW
ORK
ANALYZ
ER
R
L
50
Ω
INx
V
IN
SxA
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05743-027
NC
SxB
OFF ISOLATION =
20
log
V
OU
T
V
S
50
Ω
Figure 31. Off Isolation
V
OUT
50
Ω
NETW
O
RK
ANALYZ
ER
R
L
50
Ω
INx
V
IN
SxA
D
V
S
V
DD
V
SS
0.1µ
F
V
DD
0.1µ
F
V
SS
GND
05743-
028
NC
SxB
INSERTION LOSS = 20
log
V
OUT
WITH S
WITCH
V
OU
T
WITHOU
T SWITC
H
Figure 32
. Bandwidth
CHANNEL-T
O-
CHANNEL CROS
STAL
K = 20 l
og
V
OUT
GND
SxA
D
SxB
V
OUT
NETW
ORK
ANALYZ
ER
R
L
50
Ω
R
50
Ω
V
S
V
S
V
DD
V
SS
0.1µ
F
V
DD
0.1µ
F
V
SS
05743-02
9
INx
Figure 33. Channel
-to-Channel Crosst
alk
V
OU
T
R
S
AUDIO
PRECI
SI
O
N
R
L
10
Ω
INx
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µ
F
V
SS
GND
05743-030
Figure 34. THD + Noise
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
ADG1234YCPZ-REEL7
Mfr. #:
Buy ADG1234YCPZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs IC 80dB 120 Ohm iCMOS Dual SPST
Lifecycle:
New from this manufacturer.
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