74HC4024_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 27 November 2013 10 of 17
NXP Semiconductors
74HC4024-Q100
7-stage binary ripple counter
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
12. Waveforms
f
max
maximum frequency CP; see Figure 6
V
CC
= 2.0 V 4.0--MHz
V
CC
= 4.5 V 20--MHz
V
CC
= 6.0 V 24--MHz
Table 7. Dynamic characteristics …continued
GND = 0 V; t
r
=t
f
=6 ns; C
L
= 50 pF; see Figure 7.
Symbol Parameter Conditions Min Typ Max Unit
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to
clock (CP
) recovery time.
V
M
= 0.5 V
I
.
Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum frequency
MR input
CP input
Q0 or Qn
output
t
W
t
PHL
1/f
max
t
rec
V
M
V
M
001aab910
t
PLH
t
W
t
TLH
t
THL
t
PHL
V
M
90 % 90 %
10 % 10 %
