LT3013
13
3013fe
APPLICATIONS INFORMATION
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specifi ed with EIA temperature
characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
and temperature coeffi cients as shown in Figures 2
and 3. When used with a 5V regulator, a 16V 10µF Y5V
capacitor can exhibit an effective value as low as 1µF to
2µF for the DC bias voltage applied and over the operating
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and is
available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be signifi cant enough
to drop capacitor values below appropriate levels. Capacitor
DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verifi ed.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress, simi-
lar to the way a piezoelectric accelerometer or microphone
works. For a ceramic capacitor the stress can be induced
by vibrations in the system or thermal transients.
PWRGD Flag and Timing Capacitor Delay
The PWRGD fl ag is used to indicate that the ADJ pin volt-
age is within 10% of the regulated voltage. The PWRGD
pin is an open-collector output, capable of sinking 50µA
of current when the ADJ pin voltage is low. There is no
internal pull-up on the PWRGD pin; an external pull-up
resistor must be used. When the ADJ pin rises to within
10% of its fi nal reference value, a delay timer is started.
At the end of this delay, programmed by the value of the
capacitor on the C
T
pin, the PWRGD pin switches to a high
impedance and is pulled up to a logic level by an external
pull-up resistor.
To calculate the capacitor value on the C
T
pin, use the
following formula:
C
It
VV
TIME
CT DELAY
CT HIGH CT LOW
=
() ()
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3013 F02
20
0
–20
–40
–60
–80
–100
0
4
8
10
26
12
14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3013 F03
–25 0
50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics
LT3013
14
3013fe
APPLICATIONS INFORMATION
Figure 4 shows a block diagram of the PWRGD circuit. At
startup, the timing capacitor is discharged and the PWRGD
pin will be held low. As the output voltage increases and
the ADJ pin crosses the 90% threshold, the JK fl ip-fl op
is reset, and the 3µA current source begins to charge the
timing capacitor. Once the voltage on the C
T
pin reaches
the V
CT(HIGH)
threshold (approximately 1.7V at 25°C), the
capacitor voltage is clamped and the PWRGD pin is set to
a high impedance state.
During normal operation, an internal glitch fi lter will ignore
short transients (<15µs). Longer transients below the 90%
threshold will reset the JK fl ip-fl op. This ip-fl op ensures
that the capacitor on the C
T
pin is quickly discharged all
the way to the V
CT(LOW)
threshold before re-starting the
time delay. This provides a consistent time delay after the
ADJ pin is within 10% of the regulated voltage before the
PWRGD pin switches to high impedance.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C
for LT3013E, LT3013MP or 140°C for LT3013HFE). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential: I
OUT
• (V
IN
– V
OUT
) and,
2. GND pin current multiplied by the input voltage:
I
GND
• V
IN
.
The GND pin current can be found by examining the GND Pin
Current curves in the Typical Performance Characteristics.
Power dissipation will be equal to the sum of the two
components listed above.
The LT3013 has internal thermal limiting designed
to protect the device during overload conditions. For
continuous normal conditions the maximum junction
temperature rating of 125°C (E-grade, MP-grade) or 140°C
(H-grade)must not be exceeded. It is important to give
careful consideration to all sources of thermal resistance
from junction to ambient. Additional heat sources mounted
nearby must also be considered.
QJ
K
V
REF
• 90%
ADJ
V
CT(LOW)
~0.1V
V
CT(HIGH)
– V
BE
(~1.1V)
I
CT
3µA
C
T
3013 F04
+
+
PWRGD
Figure 4. PWRGD Circuit Block Diagram
LT3013
15
3013fe
APPLICATIONS INFORMATION
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated
by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32” FR-4 board with one ounce
copper.
Table 1. TSSOP Measured Thermal Resistance
COPPER AREA
TOPSIDE BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 40°C/W
1000 sq mm 2500 sq mm 45°C/W
225 sq mm 2500 sq mm 50°C/W
100 sq mm 2500 sq mm 62°C/W
Table 2. DFN Measured Thermal Resistance
COPPER AREA
TOPSIDE BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 40°C/W
1000 sq mm 2500 sq mm 45°C/W
225 sq mm 2500 sq mm 50°C/W
100 sq mm 2500 sq mm 62°C/W
The thermal resistance junction-to-case (θ
JC
), measured
at the exposed pad on the back of the die, is 16°C/W.
Continuous operation at large input/output voltage dif-
ferentials and maximum load current is not practical
due to thermal limitations. Transient operation at high
input/output differentials is possible. The approximate
thermal time constant for a 2500sq mm 3/32” FR-4 board
with maximum topside and backside area for one ounce
copper is three seconds. This time constant will increase
as more thermal mass is added (i.e., vias, larger board,
and other components).
For an application with transient high power peaks, average
power dissipation can be used for junction temperature
calculations if the pulse period is signifi cantly less than
the thermal time constant of the device and board.
Calculating Junction Temperature
Example 1: Given an output voltage of 5V, an input voltage
range of 8V to 12V, an output current range of 0mA to
250mA, and a maximum ambient temperature of 30°C,
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
I
OUT(MAX)
• (V
IN(MAX)
– V
OUT
) + (I
GND
• V
IN(MAX)
)
where:
I
OUT(MAX)
= 250mA
V
IN(MAX)
= 12V
I
GND
at (I
OUT
= 250mA, V
IN
= 12V) = 8mA
So:
P = 250mA • (12V – 5V) + (8mA • 12V) = 1.85W
The thermal resistance will be in the range of 40°C/W to
62°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
1.85W • 50°C/W = 92.3°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
JMAX
= 30°C + 92.3°C = 122.3°C
Example 2: Given an output voltage of 5V, an input voltage
of 48V that rises to 72V for 5ms(max) out of every 100ms,
and a 5mA load that steps to 200mA for 50ms out of
every 250ms, what is the junction temperature rise above
ambient? Using a 500ms period (well under the time
constant of the board), power dissipation is as follows:
P1(48V in, 5mA load) = 5mA • (48V – 5V)
+ (200µA • 48V) = 0.23W
P2(48V in, 50mA load) = 200mA • (48V – 5V)
+ (8mA • 48V) = 8.98W
P3(72V in, 5mA load) = 5mA • (72V – 5V)
+ (200µA • 72V) = 0.35W
P4(72V in, 50mA load) = 200mA • (72V – 5V)
+ (8mA • 72V) = 13.98W

LT3013EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 80Vin, 250mA, LDO w/ PWRGD in TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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