December 1990 2
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
FEATURES
• Various counting modes
• Asynchronous master reset
• Output capability: standard
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (
CP
0
and
CP
1
) to initiate state changes of the
counter on the HIGH-to-LOW clock
transition. State changes of the Q
n
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR
1
and MR
2
) is provided
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q
0
must be
connected externally to input CP
1
.
The input count pulses are applied to
clock input CP
0
. Simultaneous
frequency divisions of 2, 4, 8 and 16
are performed at the Q
0
, Q
1
, Q
2
and
Q
3
outputs as shown in the function
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP
1
.
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q
1
, Q
2
and Q
3
outputs. Independent use of
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF; V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CP
0
to Q
0
C
L
= 15 pF; V
CC
=5 V
12 15 ns
f
max
maximum clock frequency 100 77 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 22 22 pF
