MAX8544EEP+T Datasheet MAX8543EEE+, MAX8544EEP+, MAX8544EEP+T | P16-P18

MAX8543/MAX8544

Step-Down Controllers with Prebias Startup,

Lossless Sensing, Synchronization, and OVP

16 ______________________________________________________________________________________

Detailed Description

DC-DC Converter Control Architecture

The MAX8543/MAX8544 step-down controllers use a

PWM, current-mode control scheme. An internal

transconductance amplifier establishes an integrated

error voltage. The heart of the PWM controller is an

open-loop comparator that compares the integrated

voltage-feedback signal against the amplified current-

sense signal plus the slope-compensation ramp, which

are summed into the main PWM comparator to pre-

serve inner-loop stability and eliminate inductor stair-

casing. At each rising edge of the internal clock, the

high-side MOSFET turns on until the PWM comparator

trips or the maximum duty cycle is reached or the peak

current limit is reached. During this on-time, current

ramps up through the inductor, storing energy in a

magnetic field and sourcing current to the output. The

current-mode feedback system regulates the peak

inductor current as a function of the output-voltage-

error signal. The circuit acts as a switch-mode

transconductance amplifier and pushes the output LC

filter pole normally found in a voltage-mode PWM to a

higher frequency.

During the second half of the cycle, the high-side

MOSFET turns off and the low-side MOSFET turns on.

The inductor releases the stored energy as the current

ramps down, providing current to the output. The out-

put capacitor stores charge when the inductor current

exceeds the required load current and discharges

when the inductor current is lower, smoothing the volt-

age across the load. Under soft-overload conditions,

when the peak inductor current exceeds the selected

current limit (see the Current-Limit Circuit section), the

high-side MOSFET is turned off immediately and the

low-side MOSFET is turned on and remains on to let the

inductor current ramp down until the next clock cycle.

Under heavy-overload or short-circuit conditions, the

valley foldback current limit is enabled to reduce power

dissipation of external components.

The MAX8543/MAX8544 operate in a forced-PWM

mode. As a result, the controller maintains a constant

switching frequency, regardless of load, to allow for

easier filtering of the switching noise.

Internal 5V Linear Regulator (VL)

All MAX8543/MAX8544 functions are powered from the

on-chip, low-dropout, 5V linear regulator. Connect a

1µF to 10µF ceramic capacitor from VL to PGND. In

applications where the input voltage is less than 5.5V,

bypass the linear regulator by connecting VL to IN.

Undervoltage Lockout

When VL drops below 2.62V, the MAX8543/MAX8544

assume that the supply voltage is too low for proper oper-

ation, so the undervoltage-lockout (UVLO) circuitry

inhibits switching and forces the DL and DH gate drivers

low. When VL rises above 2.7V, the controller enters the

startup sequence and then resumes normal operation.

Startup and Soft-Start

The soft-start circuitry gradually ramps up the reference

voltage to control the rate of rise of the step-down con-

troller output and reduce input surge currents during

startup. The soft-start period is determined by the value

of the capacitor from SS to GND. The soft-start time is

approximately (33ms/µF) x C

. The MAX8543/MAX8544

also feature prebias startup; therefore, both external

power MOSFETs are kept off if the voltage at FB is higher

than that at SS. This allows the MAX8543/MAX8544 to

start up into a prebiased output without pulling the output

voltage down.

Before the MAX8543/MAX8544 can begin the soft-start

and power-up sequence, the following conditions must

be met:

1) V

exceeds the 2.7V undervoltage-lockout threshold.

2) EN is at logic high.

3) The thermal limit is not exceeded.

Enable

The MAX8543/MAX8544 feature a low-power shutdown

mode. A logic low at EN shuts down the controller.

During shutdown, the output is high impedance, and

both DH and DL are low. Shutdown reduces the quies-

cent current (I

) to less than 10µA. A logic high at EN

enables the controller.

Synchronous-Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in

the rectifier by replacing the normal Schottky catch

diode with a low-resistance MOSFET switch. The

MAX8543/MAX8544 also use the synchronous rectifier

to ensure proper startup of the boost gate-driver circuit

and to provide the current-limit signal. The DL low-side

gate-drive waveform is always the complement of the

DH high-side gate-drive waveform (with controlled

dead time to prevent cross-conduction or shoot-

through). An adaptive dead-time circuit monitors the DL

voltage and prevents the high-side MOSFET from turn-

ing on until DL is fully off. For the dead-time circuit to

work properly, there must be a low-resistance, low-

inductance path from the DL driver to the MOSFET

gate. Otherwise, the sense circuitry in the MAX8543/

MAX8544 can interpret the MOSFET gate as off when

gate charge actually remains.

MAX8543/MAX8544

Step-Down Controllers with Prebias Startup,

Lossless Sensing, Synchronization, and OVP

______________________________________________________________________________________ 17

Use very short, wide traces, about 10 to 20 squares

(50 mils to 100 mils wide if the MOSFET is 1in from the

device) for the gate drive. The dead time at the other

edge (DH turning off) also has an adaptive dead-time

circuit operating in a similar manner. For both edges,

there is an additional fixed dead time after the adaptive

dead time expires.

High-Side Gate-Drive Supply (BST)

A flying capacitor boost circuit (Figure 3) generates the

gate-drive voltage for the high-side n-channel MOSFET.

The capacitor between BST and LX is charged from VL

up to V

minus the diode forward-voltage drop while the

low-side MOSFET is on. When the low-side MOSFET is

switched off, the stored voltage of the capacitor is

stacked above LX to provide the necessary turn-on

voltage (V

) for the high-side MOSFET. The controller

then closes an internal switch between BST and DH to

turn the high-side MOSFET on.

Current-Sense Amplifier

The MAX8543/MAX8544 current-sense circuit amplifies

the differential current-sense voltage (V

CS+

- V

CS-

). The

gain of the current-sense amplifier is determined by the

states of ILIM and ILIM1. This amplified current-sense

signal and the internal slope-compensation signal are

summed (V

SUM

) together and fed into the PWM com-

parator’s inverting input. The PWM comparator shuts

off the high-side MOSFET when V

SUM

exceeds the

integrated feedback voltage (V

COMP

The differential current sense is also used to provide

peak inductor current limiting. This current limit is more

accurate than the valley current limit, which is measured

across the low-side MOSFET’s on-resistance.

Current-Limit Circuit

The MAX8543/MAX8544 use both valley foldback current

limiting and peak constant current limiting, simultaneously

(Figure 4). The valley foldback current limit is used to

reduce power dissipation of external components, mainly

inductor and power MOSFETs, and upstream power

source, when output is severely overloaded or short

circuited. Thus the circuit can withstand short-circuit

conditions indefinitely without causing overheating of any

component. The peak constant current limit sets the cur-

rent-limit point more accurately since it does not have to

suffer the wide variation of the low-side power MOSFET’s

on-resistance due to tolerance and temperature.

The valley current is sensed across the on-resistance of

the low-side MOSFET (V

PGND

- V

). The valley current

limit trips when the sensed current exceeds the valley

current-limit threshold. The valley current limit recovers

when the sensed current drops below the valley current-

limit threshold (except when using the latch-off option

with the MAX8544).

Set the minimum valley current-limit threshold, when the

output voltage is at a nominal regulated value, higher

than the maximum peak current-limit setting. With this

method, the current-limit point accuracy is controlled by

the peak current limit and is not interfered with by the

wide variation of MOSFET on-resistance. See the Setting

the Current Limits section for how to set these limits.

The MAX8543 has a fixed valley current-limit threshold

and fixed foldback ratio. The MAX8544 can select

between an adjustable valley current-limit threshold

with adjustable foldback ratio and a fixed valley current

limit without foldback for latch-off. When latch-off is

used (MODE is connected to VL), set the current-limit

threshold by only one resistor from ILIM2 to GND and

make sure this threshold is higher than the maximum

output current required by at least a 20% margin. Cycle

EN or input power to reset the current-limit latch.

The peak current limit is used to sense the inductor

current, and is more accurate than the valley current limit

since it does not depend upon the on-resistance of the

low-side MOSFET. The peak current can be measured

across the resistance of the inductor for the highest

efficiency, or alternatively, a current-sense resistor can

be used for more accurate current sensing. The

MAX8543/MAX8544 have four selectable peak current-

limit thresholds that are selected using ILIM (MAX8543)

or ILIM1 (MAX8544). See Table 3 for the current-limit

settings.

For more information on the current limit, see the

Setting the Current Limits section.

MAX8543/

MAX8544

BST

Figure 3. The boost circuit provides voltage for the high-side

MOSFET gate drive.

MAX8543/MAX8544

Step-Down Controllers with Prebias Startup,

Lossless Sensing, Synchronization, and OVP

18 ______________________________________________________________________________________

Switching Frequency and

Synchronization

The MAX8543/MAX8544 have an adjustable internal

oscillator that can be set to any frequency from 200kHz

to 1MHz. To set the switching frequency, connect a

resistor from FSYNC to GND. Calculate the resistor

value from the following equation:

The MAX8543/MAX8544 can also be synchronized to an

external clock by connecting the clock signal to FSYNC.

When using an external clock, select R

FSYNC

such that

the free-running frequency is within ±30% of the clock fre-

quency. In addition, the MAX8544 has a synchronization

output (SYNCO) that provides a clock signal that is 180°

out-of-phase with the MAX8544 switching. SYNCO is

used to synchronize a second controller 180° out-of-

phase with the first by connecting SYNCO of the first con-

troller to FSYNC of the second when the first controller

operates in free-running mode. When the first controller is

synchronized to an external clock, the external clock is

inverted to generate SYNCO.

Power-Good Signal (POK)

POK is an open-drain output on the MAX8544 that moni-

tors the output voltage. When the output is above 91% of

its nominal regulation voltage, POK is high impedance.

When the output drops below 91% of its nominal regula-

tion voltage, POK is pulled low. POK is also pulled low

when the MAX8544 is shut down. To use POK as a logic-

level signal, connect a pullup resistor from POK to the

logic-supply rail.

Thermal-Overload Protection

Thermal-overload protection limits total power dissipation

in the MAX8543/MAX8544. When the junction tempera-

ture exceeds T

= +160°C, an internal thermal sensor

shuts down the device, allowing the IC to cool. The ther-

mal sensor turns the IC on again after the junction tem-

perature cools by 15°C, resulting in a pulsed output

during continuous thermal-overload conditions.

Design Procedure

Setting the Output Voltage

To set the output voltage for the MAX8543/MAX8544,

connect FB to the center of an external resistor-divider

from the output to GND (Figure 5). Select R2 between

8kΩ and 24kΩ; then calculate R1 with the following

equation:

where V

= 0.8V. R1 and R2 should be placed as

close to the IC as possible.

Inductor Selection

There are several parameters that must be examined

when determining which inductor is to be used: input volt-

age, output voltage, load current, switching frequency,

and LIR. LIR is the ratio of peak-to peak inductor current

ripple to maximum DC load current. A higher LIR value

allows for a smaller inductor, but results in higher losses

and higher output ripple.

OUT

12 1=× −

⎛

⎝

⎜

⎞

⎠

⎟

FSYNC

=−

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

240

14 18

TIME

INDUCTOR CURRENT

VALLEY

LOAD

PEAK

Figure 4. Inductor-Current Waveform

MAX8543/

MAX8544

Figure 5. Setting the Output Voltage with a Resistor Voltage-

Divider

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MAX8544EEP+T

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Switching Controllers Step-Down Controller

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