SCC2681AC1A44,512 Datasheet SCC2681AE1A44,512, SCC2681AC1A44,512, SCC2681AE1A44,518 | P16-P18

Philips Semiconductors Product data

SCC2681Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

CSRA[7:4] – Channel A Receiver Clock Select

This field selects the baud rate clock for the Channel A receiver as

follows (X1 rate at 3.6864 MHz):

CSRA[7:4]

ACR[7] = 0

Baud Rate

ACR[7] = 1

0000 50 75

0001 110 110

0010 134.5 134.5

0011 200 150

0100 300 300

0101 600 600

0110 1,200 1,200

0111 1,050 2,000

1000 2,400 2,400

1001 4,800 4,800

1010 7,200 1,800

1011 9,600 9,600

1100 38.4k 19.2k

1101 Timer Timer

1110 IP4–16× IP4–16×

1111 IP4–1× IP4–1×

(See also Table 5 for other rates to 115.2 kHz)

Rates will change in direct proportion to X1 at 3.6864 MHz.

The receiver clock is always a 16× clock except for CSRA[7] = 1111.

CSRA[3:0] – Channel A Transmitter Clock Select

This field selects the baud rate clock for the Channel A transmitter.

The field definition is as per CSR[7:4] except as follows:

CSRA[3:0]

ACR[7] = 0

Baud Rate

ACR[7] = 1

1110

1111

IP3–16×

IP3–1×

IP3–16×

IP3–1×

The transmitter clock is always a 16× clock except for

CSR[3:0] = 1111.

CSRB – Channel B Clock Select Register

CSRB[7:4] – Channel B Receiver Clock Select

This field selects the baud rate clock for the Channel B receiver. The

field definition is as per CSRA[7:4] except as follows:

CSRB[7:4]

ACR[7] = 0

Baud Rate

ACR[7] = 1

1110

1111

IP6–16×

IP6–1×

IP6–16×

IP6–1×

The receiver clock is always a 16× clock except for CSRB[7:4] = 1111.

CSRB[3:0] – Channel B Transmitter Clock Select

This field selects the baud rate clock for the Channel B transmitter.

The field definition is as per CSRA[7:4] except as follows:

CSRB[3:0]

ACR[7] = 0

Baud Rate

ACR[7] = 1

1110

1111

IP5–16×

IP5–1×

IP5–16×

IP5–1×

The transmitter clock is always a 16× clock except for

CSRB[3:0] = 1111.

CRA – Channel A Command Register

CRA is a register used to supply commands to Channel A. Multiple

commands can be specified in a single write to CRA as long as the

commands are non-conflicting, e.g., the ‘enable transmitter’ and

‘reset transmitter’ commands cannot be specified in a single

command word.

CRA[7] – Not Used

Must be set to zero.

CRA[6:4] – Channel A Miscellaneous Command

The encoded value of this field may be used to specify a single

command as follows:

CRA[6:4] – COMMAND

000 No command.

001 Reset MR pointer. Causes the Channel A MR pointer to point

to MR1.

010 Reset receiver. Resets the Channel A receiver as if a hard-

ware reset had been applied. The receiver is disabled and the

FIFO is flushed.

011 Reset transmitter. Resets the Channel A transmitter as if a

hardware reset had been applied.

100 Reset error status. Clears the Channel A Received Break,

Parity Error, and Overrun Error bits in the status register

(SRA[7:4]). Used in character mode to clear OE status (al-

though RB, PE and FE bits will also be cleared) and in block

mode to clear all error status after a block of data has been

received.

101 Reset Channel A break change interrupt. Causes the Chan-

nel A break detect change bit in the interrupt status register

(ISR[2]) to be cleared to zero.

110 Start break. Forces the TxDA output LOW (spacing). If the

transmitter is empty the start of the break condition will be

delayed up to two bit times. If the transmitter is active the

break begins when transmission of the character is com-

pleted. If a character is in the THR, the start of the break will

be delayed until that character, or any other loaded subse-

quently are transmitted. The transmitter must be enabled for

this command to be accepted.

111 Stop break. The TxDA line will go HIGH (marking) within two

bit times. TxDA will remain HIGH for one bit time before the

next character, if any, is transmitted.

CRA[3] – Disable Channel A Transmitter

This command terminates transmitter operation and reset the

TxDRY and TxEMT status bits. However, if a character is being

transmitted or if a character is in the THR when the transmitter is

disabled, the transmission of the character(s) is completed before

assuming the inactive state. A disable transmitter cannot be loaded.

CRA[2] – Enable Channel A Transmitter

Enables operation of the Channel A transmitter. The TxRDY status

bit will be asserted.

CRA[1] – Disable Channel A Receiver

This command terminates operation of the receiver immediately – a

character being received will be lost. The command has no effect on

the receiver status bits or any other control registers. If the special

multidrop mode is programmed, the receiver operates even if it is

disabled. See Operation section.

CRA[0] – Enable Channel A Receiver

Enables operation of the Channel A receiver. If not in the special

wake up mode, this also forces the receiver into the search for

start-bit state.

Note: Performing disable and enable at the same time results in

disable.

Philips Semiconductors Product data

SCC2681Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

CRB – Channel B Command Register

CRB is a register used to supply commands to Channel B. Multiple

commands can be specified in a single write to CRB as long as the

commands are non-conflicting, e.g., the ‘enable transmitter’ and

‘reset transmitter’ commands cannot be specified in a single

command word.

The bit definitions for this register are identical to the bit definitions

for CRA, except that all control actions apply to the Channel B

receiver and transmitter and the corresponding inputs and outputs.

SRA – Channel A Status Register

SRA[7] – Channel A Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxDA line to the marking state for at

least one-half a bit, time two successive edges of the internal or

external 1× clock. This will usually require a HIGH time of one 1×

clock period or 3 1× edges since the clock of the controller is not

synchronous to the 1× clock.

When this bit is set, the Channel A ‘change in break’ bit in the ISR

(ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected.

The break detect circuitry can detect breaks that originate in the

middle of a received character. However, if a break begins in the

middle of a character, it must persist until at least the end of the next

character time in order for it to be detected.

SRA[6] – Channel A Framing Error

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first bit position.

SRA[5] – Channel A Parity Error

This bit is set when the ‘with parity’ or ‘force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity.

In the special multidrop mode the parity error bit stores the receive

A/D bit.

SRA[4] – Channel A Overrun Error

This bit, when set indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the FIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost.

This bit is cleared by a ‘reset error status’ command.

SRA[3] – Channel A Transmitter Empty (TxEMTA)

This bit will be set when the transmitter underruns, i.e., both the

TxEMT and TxRDY bits are set. This bit and TxRDY are set when

the transmitter is first enabled and at any time it is re-enabled after

either (a) reset, or (b) the transmitter has assumed the disabled

state. It is always set after transmission of the last stop bit of a

character if no character is in the THR awaiting transmission.

It is reset when the THR is loaded by the CPU, a pending

transmitter disable is executed, the transmitter is reset, or the

transmitter is disabled while in the underrun condition.

SRA[2] – Channel A Transmitter Ready (TxRDYA)

This bit, when set, indicates that the THR is empty and ready to be

loaded with a character. This bit is cleared when the THR is loaded

by the CPU and is set when the character is transferred to the

transmit shift register. TxRDY is reset when the transmitter is

disabled or reset, and is set when the transmitter is first enabled,

viz., characters loaded into the THR while the transmitter is disabled

will not be transmitted.

SRA[1] – Channel A FIFO Full (FFULLA)

This bit is set when a character is transferred from the receive shift

become full, i.e., all three FIFO positions are occupied. It is reset

when the CPU reads the RHR. If a character is waiting in the

receive shift register because the FIFO is full, FFULL will not be

reset when the CPU reads the RHR.

SRA[0] – Channel A Receiver Ready (RxRDYA)

This bit indicates that a character has been received and is waiting

in the FIFO to be read by the CPU. It is set when the character is

transferred from the receive shift to the FIFO and reset when the

CPU reads the RHR, if after this read there are not more characters

still in the FIFO.

SRB – Channel B Status Register

The bit definitions for this register are identical to the bit definitions

for SRA, except that all status applies to the Channel B receiver and

transmitter and the corresponding inputs and outputs.

Philips Semiconductors Product data

SCC2681Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

OPCR – Output Port Configuration Register

OPCR[7] – OP7 Output Select

This bit programs the OP7 output to provide one of the following:

0 – The complement of OPR[7].

1 – The Channel B transmitter interrupt output which is the

complement of TxRDYB. When in this mode OP7 acts as an

Open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[6] – OP6 Output Select

This bit programs the OP6 output to provide one of the following:

0 – The complement of OPR[6].

1 – The Channel A transmitter interrupt output which is the

complement of TxRDYA. When in this mode OP6 acts as an

Open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[5] – OP5 Output Select

This bit programs the OP5 output to provide one of the following:

0 – The complement of OPR[5].

1 – The Channel B transmitter interrupt output which is the

complement of ISR[5]. When in this mode OP5 acts as an

Open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[4] – OP4 Output Select

This field programs the OP4 output to provide one of the following:

0 – The complement of OPR[4].

1 – The Channel B transmitter interrupt output which is the

complement of ISR[1]. When in this mode OP4 acts as an

Open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[3:2] – OP3 Output Select

This bit programs the OP3 output to provide one of the following:

00 – The complement of OPR[3].

01 – The counter/timer output, in which case OP3 acts as an

Open-drain output. In the timer mode, this output is a square

wave at the programmed frequency. In the counter mode, the

output remains HIGH until terminal count is reached, at which

time it goes LOW. The output returns to the HIGH state when

the counter is stopped by a stop counter command. Note that

this output is not masked by the contents of the IMR.

10 – The 1× clock for the Channel B transmitter, which is the clock

that shifts the transmitted data. If data is not being transmitted,

a free running 1× clock is output.

11 – The 1× clock for the Channel B receiver, which is the clock that

samples the received data. If data is not being received, a free

running 1× clock is output.

OPCR[1:0] – OP2 Output Select

This field programs the OP2 output to provide one of the following:

00 – The complement of OPR[2].

01 – The 16× clock for the Channel A transmitter. This is the clock

selected by CSRA[3:0], and will be a 1× clock if

CSRA[3:0] = 1111.

10 – The 1× clock for the Channel A transmitter, which is the clock

that shifts the transmitted data. If data is not being transmitted,

a free running 1× clock is output.

11 – The 1× clock for the Channel A receiver, which is the clock that

samples the received data. If data is not being received, a free

running 1× clock is output.

ACR – Auxiliary Control Register

ACR[7] – Baud Rate Generator Set Select

This bit selects one of two sets of baud rates to be generated by the

BRG:

Set 1: 50, 110, 134.5, 200, 300, 600, 1.05 k, 1.2 k, 2.4 k, 4.8 k,

7.2 k, 9.6 k, and 38.4 k baud.

Set 2: 75, 110, 134.5, 150, 300, 600, 1.2 k, 1.8 k, 2.0 k, 2.4 k,

4.8 k, 9.6 k, and 19.2 k baud.

Please see Table 5 for rates to 115.2 k baud.

The selected set of rates is available for use by the Channel A and

B receivers and transmitters as described in CSRA and CSRB.

Baud rate generator characteristics are given in Table 3.

ACR[6:4] – Counter/Timer Mode And Clock Source Select

This field selects the operating mode of the counter/timer and its

clock source as shown in Table 4.

Table 4. ACR 6:4 Field Definition

ACR 6:4 MODE CLOCK SOURCE

000 Counter External (IP2)

001 Counter TxCA – 1× clock of Channel A

transmitter

010 Counter TxCB – 1× clock of Channel B

transmitter

011 Counter Crystal or external clock (X1/CLK)

divided by 16

100 Timer

(square wave)

External (IP2)

101 Timer

(square wave)

External (IP2) divided by 16

110 Timer

(square wave)

Crystal or external clock (X1/CLK)

111 Timer

(square wave)

Crystal or external clock (X1/CLK)

divided by 16

NOTE: Timer mode generates a squarewave.

ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable

This field selects which bits of the input port change register (IPCR)

cause the input change bit in the interrupt status register (ISR[7]) to

be set. If a bit is in the ‘on’ state the setting of the corresponding bit

in the IPCR will also result in the setting of ISR[7], which results in

the generation of an interrupt output if IMR[7] = 1. If a bit is in the

‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].

IPCR – Input Port Change Register

IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State

These bits are set when a change-of-state, as defined in the input

port section of this data sheet, occurs at the respective input pins.

They are cleared when the IPCR is read by the CPU. A read of

the IPCR also clears ISR[7], the input change bit in the interrupt

status register. The setting of these bits can be programmed to

generate an interrupt to the CPU.

IPCR[3:0] – IP3, IP2, IP1, IP0 Current State

These bits provide the current state of the respective inputs. The

information is unlatched and reflects the state of the input pins at the

time the IPCR is read.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

SCC2681AC1A44,512

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UART Interface IC RPLACMNT FOR SCN2681

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SCC2681AC1A44,512

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