LTC2942
13
2942fa
applicaTions inFormaTion
dressed is considered a slave. The LTC2942 always acts
as a slave.
Figure 3 shows an overview of the data transmission for
fast and standard mode on the I
2
C bus.
START and STOP Conditions
When the bus is idle, both SCL and SDA must be HIGH. A
bus master signals the beginning of a transmission with a
START condition by transitioning SDA from HIGH to LOW
while SCL is HIGH. When the master has finished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is then free for another transmission. When
the bus is in use, it stays busy if a repeated START (Sr)
is generated instead of a STOP condition. The repeated
START (Sr) conditions are functionally identical to the
START (S).
Data Transmission
After a START condition, the I
2
C bus is considered busy
and data transfer begins between a master and a slave.
As data is transferred over I
2
C in groups of nine bits
(eight data bits followed by an acknowledge bit), each
group takes nine SCL cycles. The transmitter releases
the SDA line during the acknowledge clock pulse and the
receiver issues an acknowledge (ACK) by pulling SDA
LOW or leaves SDA HIGH to indicate a not acknowledge
(NACK) condition. Change of data state can only happen
while SCL is LOW.
Write Protocol
The master begins a write operation with a START condi-
tion followed by the seven bit slave address 1100100
and the R/W bit set to zero, as shown in Figure 4. The
LTC2942 acknowledges this by pulling SDA LOW and
then the master sends a command byte which indicates
which internal register the master is to write. The LTC2942
acknowledges and latches the command byte into its
internal register address pointer. The master delivers the
data byte, the LTC2942 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
master continues by sending a second data byte instead
of a STOP, the LTC2942 acknowledges again, increments
its address pointer and latches the second data byte in
the following register, as shown in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
2942 F03
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
Figure 3. Data Transfer Over I
2
C or SMBus
FROM MASTER TO SLAVE
S W
ADDRESS REGISTER DATA
FROM SLAVE TO MASTER
2942 F04
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
A A A
0
1100100 01h FCh
0 0 0
P
Figure 4. Writing FCh to the LTC2942 Control Register (B)
S W
ADDRESS REGISTER DATA
2942 F05
A A A
0
1100100 02h F0h 01h
0 0 0
0
P
DATA
A
Figure 5. Writing F001h to the LTC2942
Accumulated Charge Register (C, D)
