LTC2942
4
2942fa
Timing Diagram
t
SU, DAT
t
SU, STO
t
SU, STA
t
BUF
t
HD, STA
t
HD, DATO,
t
HD, DATI
t
HD, STA
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
SDA
SCL
2942 F01
t
of
Figure 1. Definition of Timing on I
2
C Bus
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
HD,DATO
Data Hold Time Output
l
0.3 0.9 µs
t
OF
Data Output Fall Time (Notes 7, 8)
l
20 + 0.1 • C
B
300 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified
Note 3: I
SUPPLY
= I
SENSE
+
+ I
SENSE
–
Note 4: The equivalent charge of an LSB in the accumulated charge
register depends on the value of R
SENSE
and the setting of the internal
prescaling factor M:
q
LSB
= 0.085mAh •
R
SENSE
•
128
See Choosing R
SENSE
and Choosing Coulomb Counter Prescaler M section
for more information. 1mAh = 3.6C (coulombs).
Note 5: Deviation of q
LSB
from its nominal value.
Note 6: The quantization step of the 14-bit ADC in voltage mode and
10-bit ADC in temperature mode is not to be mistaken with the LSB of the
combined 16-bit voltage registers (I, J) and 16-bit temperature registers
(M, N).
Note 7: C
B
= Capacitance of one bus line in pF (10pF ≤ C
B
≤ 400pF). See
Voltage and Temperature Registers section for more information.
Note 8: Guaranteed by design, not subject to test.
