REV. B
AD8041
–11–
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 4, the AD8041 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
5.0V
2.5V
0V
40ns50mV
OUTPUT
INPUT
G = +2
V
S
= 5V
Figure 4. Overdrive Recovery
Circuit Description
The AD8041 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with similar
f
T
in the 2 GHz to 4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features allow the construction of
high frequency, low distortion amplifiers with low supply currents.
This design uses a differential output input stage to maximize
bandwidth and headroom (see Figure 5). The smaller signal
swings required on the first stage outputs (nodes S1P, S1N) reduce
the effect of nonlinear currents due to junction capacitances and
improve the distortion performance. With this design harmonic
distortion of better than –85 dB @ 1 MHz into 100 with V
OUT
=
2 V p-p (Gain = +2) on a single 5 V supply is achieved.
The complementary common-emitter design of the output stage
provides excellent load drive without the need for emitter follow-
ers, thereby improving the output range of the device consider-
ably with respect to conventional op amps. High output drive
capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5,
along with a common-mode feedback loop (not shown). This
circuit topology allows the AD8041 to drive 50 mA of output
current with the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Exceed-
ing these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
A “Nested Integrator” topology is used in the AD8041 (see
the small-signal schematic in Figure 6). The output stage can
be modeled as an ideal op amp with a single-pole response and
a unity-gain frequency set by transconductance g
m2
and
Capacitor C9. R1 is the output resistance of the input stage; g
m
is the input transconductance. C7 and C9 provide Miller com-
pensation for the overall op amp. The unity gain frequency will
occur at g
m
/C9. Solving the node equations for this circuit yields:
V
Vi
A
sR C A s
g
C
OUT
m
=
++×
+
0
19 21 1
3
1
2
([( )])
where A0 = g
m
g
m2
R2 R1 (Open-Loop Gain of Op Amp)
A2 = g
m2
R2 (Open-Loop Gain of Output Stage)
The first pole in the denominator is the dominant pole of the
amplifier and occurs at about 180 Hz. This equals the input
stage output impedance R1 multiplied by the Miller-multiplied
value of C9. The second pole occurs at the unity-gain bandwidth
of the output stage, which is 250 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard two-stage architecture would allow.
Output Impedance
The low frequency open-loop output impedance of the common
emitter output stage used in this design is approximately 6.5 k.
While this is significantly higher than a typical emitter follower
output stage, when connected with feedback, the output imped-
ance is reduced by the open-loop gain of the op amp. With
110 dB of open-loop gain, the output impedance is reduced
to less than 0.1 . At higher frequencies, the output impedance
will rise as the open-loop gain of the op amp drops; however, the
output also becomes capacitive due to the integrator capacitors
C9 and C3. This prevents the output impedance from ever becom-
ing excessively high (see TPC 15), which can cause stability
problems when driving capacitive loads. In fact, the AD8041
has excellent cap-load drive capability for a high frequency op
amp. TPC 22 demonstrates that the AD8041exhibits a 45°
margin while driving a 20 pF direct capacitive load. In addition,
running the part at higher gains will also improve the capacitive
load drive capability of the op amp.
S1N
R21
R3
V
EE
Q11
Q3
I10
R26 R39
Q5
Q4
Q40
I7
R2R15
Q13
Q17
R5
C7
Q2
S1P
Q22
Q7
Q21
Q24
R23
R27
I2 I3
I1
Q51
Q25
Q50
Q39
Q47
Q27
Q31
Q23
I9
I5
V
EE
V
CC
I8
Q36
Q8
V
OUT
C3
C9
V
CC
V
IN
P
V
IN
N
V
EE
Figure 5. AD8041 Simplified Schematic
REV. B–12–
AD8041
R2
C3
g
m2
V
OUT
R1
C9
g
m
Vi
S1N
S1P
C7
R1
g
m
Vi
Figure 6. Small Signal Schematic
Disable Operation
The AD8041 has an active-low disable pin, which can be used
to three-state the output of the part and also lower its supply
current. If the disable pin is left floating, the part is enabled and
will perform normally. If the disable pin is pulled to 2.5 V (min)
below the positive supply, output of the AD8041 will be disabled
and the nominal supply current will drop to less than 1.6 mA.
For best isolation, the disable pin should be pulled to as low a
voltage as possible; ideally, the negative supply rail.
The disable pin on the AD8041 allows it to be configured as a 2:1
mux as shown in Figure 7 and can be used to switch many types of
high speed signals. Higher order multiplexers can also be built.
The break-before-make switching time is approximately 50 ns to
disable the output and 300 ns to enable the output.
6
4
7
3
2
AD8041
330
50
10F
5V
330
8
6
4
7
3
2
AD8041
330
50
10F
5V
330
8
13
12 11
10
74HC04
50
G = +2
G = +2
CH0
5MHz
CH1
10MHz
Figure 7. 2:1 Multiplexer
10
0%
100
90
200ns
1V
V
S
= 5V
Figure 8. 2:1 Multiplexer Performance
Single-Supply A/D Conversion
Figure 9 shows the AD8041 driving the analog inputs of the
AD9050 in a dc-coupled system with single-ended signals. All
components are powered from a single 5 V supply. The AD820
is used to offset the ground referenced input signal to the level
required by the AD9050. The AD8041 is used to add in the offset
with the ground referenced input signal and buffer the input to
AD9050. The nominal input range of the AD9050 is 2.8 V
and 3.8 V (1 V p-p centered at 3.3 V). This circuit provides
40 MSPS analog-to-digital conversion on just 330 mW of power
while delivering 10-bit performance.
0.1F
5V
AD8041
2.8V – 3.8V
3.3V
5V
AD9050
10
9
1k
V
IN
–0.5V TO +0.5V
1k1k
0.1F
5V
AD820
1k
Figure 9. 10-Bit, 40 MSPS A/D Conversion
0
–10
–100
–60
–70
–80
–90
–40
–50
–30
–20
F
1
= 4.9MHz
FUNDAMENTAL = 0.6dB
SECOND HARMONIC = 66.9dB
THIRD HARMONIC = 74.7dB
SNR = 55.2dB
NOISE FLOOR = – 86.1dB
ENCODE FREQUENCY = 40MHz
Figure 10. FFT Output of Circuit in Figure 9
REV. B
AD8041
–13–
APPLICATIONS
RGB Buffer
The AD8041 can provide buffering of RGB signals that include
ground while operating from a single 3 V or 5 V supply.
The signals that drive an RGB monitor are usually supplied by
current output DACs that operate from a 5 V only supply. These
can triple DACs like the ADV7120 and ADV7122 from Analog
Devices or integrate into the graphics controller IC as in most
PCs these days.
During the horizontal blanking interval, the currents output
from the DACs go to zero and the RGB signals are pulled to
ground via the termination resistors. If more than one RGB
monitor is desired, it cannot simply be connected in parallel
because it will provide an additional termination. Therefore,
buffering must be provided before connecting a second monitor.
Since the RGB signals include ground as part of their dynamic
output range, it has previously been required to use a dual-
supply op amp to provide this buffering. In some systems, this is
the only component that requires a negative supply, so it can be
quite inconvenient to incorporate this multiple monitor feature.
Figure 11 shows a schematic of one channel of a single-supply,
gain-of-two buffer for driving a second RGB monitor. No cur-
rent is required when the amplifier output is at ground. The
termination resistor at the monitor helps pull the output down
at low voltage levels.
6
4
7
3
2
AD8041
1k
75
10F
8
75
R, G OR B
NC
0.1F
1k
PRIMARY RGB
MONITOR
75
SECOND RGB
MONITOR
3V OR 5V
Figure 11. Single-Supply RGB Buffer
Figure 12 is an oscilloscope photo of the circuit in Figure 11
operating from a 3 V supply and driven by the blue signal of a
color bar pattern. Note that the input and output are at ground
during the horizontal blanking interval. The RGB signals are
specified to output a maximum of 700 mV peak. The output of
the AD8041 is 1.4 V with the termination resistors providing a
divide-by-two. The red and green signals can be buffered in the
same manner with duplication of this circuit.
V
IN
GND
GND
V
OUT
10
0%
100
90
5
s500mV
500mV
Figure 12. 3 V, RGB Buffer
Single-Supply Composite Video Line Driver
Figure 13 shows a schematic of a single-supply gain-of-two
composite video line driver. Since the sync tips of a composite
video signal extend below ground, the input must be ac-coupled
and shifted positively to provide signal swing during these nega-
tive excursions in a single-supply configuration.
The input is terminated in 75 and ac-coupled via C
IN
to a
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding of
the nature of composite video signals and the video performance
of the AD8041.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-to-
peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required will approach twice the peak-to-peak value.
The two bounding cases are for a duty cycle that is mostly low,
but occasionally goes high at a fraction of a percent duty cycle
and vice versa.
Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame
but has a white (full intensity), minimum width spike at least
once per frame.
The other extreme is for a video signal that is full white every-
where. The blanking intervals and sync tips of such a signal will
have negative going excursions in compliance with composite
video specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at its highest level
(white) for only about 75% of the time.
As a result of the duty cycle variations between the two extremes
presented above, a 1 V p-p composite video signal that is multi-
plied by a gain of two requires about 3.2 V p-p of dynamic voltage
swing at the output for an op amp to pass a composite video
signal of arbitrary duty cycle without distortion.
Some circuits use a sync tip clamp along with ac coupling to
hold the sync tips at a relatively constant level in order to lower
the amount of dynamic signal swing required. However, these
circuits can have artifacts like sync tip compression unless they
are driven by sources with very low output impedance.
6
4
7
3
2
AD8041
R
F
1k
10k
10F
5V
75
COMPOSITE
VIDEO IN
NC
0.1F
R
T
75
8
1000F
0.1F
4.99k
10F
4.99k
47F
R
G
1k
220F
75
COAX
R
L
75
V
OUT
Figure 13. Single-Supply Composite Video Line Driver
The AD8041 not only has ample signal swing capability to
handle the dynamic range required without using a sync tip
clamp but also has good video specifications like differential
gain and differential phase when buffering these signals in an ac-
coupled configuration.

AD8041ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 160MHz RR w/ Disable
Lifecycle:
New from this manufacturer.
Delivery:
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