7
FN6093.3
February 27, 2013
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. C
L
includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. C
L
includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
50%
t
r
< 20ns
t
f
< 20ns
t
OFF
90%
V+
0V
V
NO
0V
t
ON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
V
OUT
V
OUT
V
(NO or NC)
R
L
R
L
R
ON
+
------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
V
OUT
R
L
C
L
COM
NO or NC
IN
50
35pF
GND
V+
C
V
OUT
V
OUT
ON
OFF
ON
Q = V
OUT
x C
L
SWITCH
OUTPUT
LOGIC
INPUT
V+
0V
C
L
V
OUT
R
G
V
G
GND
COM
NO or NC
V+
C
LOGIC
INPUT
IN
Repeat test for all switches.
90%
V+
0V
t
D
LOGIC
INPUT
SWITCH
OUTPUT
0V
V
OUT
LOGIC
INPUT
IN
COM
R
L
C
L
V
OUT
35pF
50
NO
NC
V+
GND
V
NX
C
ISL43L220
8
FN6093.3
February 27, 2013
Detailed Description
The ISL43L220 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.1V to 4.5V supply with low on-
resistance (0.22) and high speed operation (t
ON
=11ns,
t
OFF
= 5ns). The device is especially well suited for portable
battery powered equipment due to its low operating supply
voltage (1.1V), low power consumption (4.5W max), low
leakage currents (110nA max), and the tiny DFN package.
The ultra low on-resistance and Ron flatness provide very low
insertion loss and distortion to applications that require signal
reproduction.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
ON
TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
ANALYZER
R
L
SIGNAL
GENERATOR
V+
C
0V or V+
NO or NC
COM
IN
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
0V or V+
NO or NC
COM
IN
GND
V
NX
V
1
R
ON
= V
1
/100mA
100mA
Repeat test for all switches.
0V or V+
ANALYZER
V+
C
NO or NC
SIGNAL
GENERATOR
R
L
GND
IN
1
COM
50
N.C.
COM
NC or NO
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or V+
Repeat test for all switches.
ISL43L220
9
FN6093.3
February 27, 2013
purpose of using a low R
ON
switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
Power-Supply Considerations
The ISL43L220 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L220 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.1V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (see Figure 16). At 3.6V
the V
IH
level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see
Figure 19). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 20 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
FIGURE 8. OVERVOLTAGE PROTECTION
GND
V
COM
V
NO or NC
OPTIONAL PROTECTION
V+
IN
X
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL43L220

ISL43L220IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs ANALO SWITCH DL SPDT 0 4OHM S 1 2V 4 5V
Lifecycle:
New from this manufacturer.
Delivery:
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