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MC74ACT652NG

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 7
1 Publication Order Number:
MC74AC652/D
MC74AC652, MC74ACT652
Octal Transceiver/Register
with 3-State Outputs
(Non-Inverting)
The MC74AC/ACT652 consists of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated in Figures 1 to 4.
Features
• Independent Registers for A and B Buses
• Multiplexed Real−Time and Stored Data Transfers
• Choice of True and Inverting Data Paths
• 3−State Outputs
• 300 mil Slim Dual−in−Line Package
• Outputs Source/Sink 24 mA
• ′ACT652 Has TTL Compatible Inputs
• These are Pb−Free Devices
www.onsemi.com
MARKING DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
SO−24
DW SUFFIX
CASE 751E
ACT652
AWLYYWWG
1
24
AC652
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
TRANSFER
FROM REGISTER TO BUS
REG REG
A‐BUS
B‐BUS
REAL TIME TRANSFER
A‐BUS TO B‐BUS
REG REG
A‐BUS
B‐BUS
REAL TIME TRANSFER
B‐BUS TO A‐BUS
REG REG
A‐BUS
B‐BUS
Figure 1. Figure 2.
STORAGE
FROM BUS TO REGISTER
REG REG
A‐BUS
B‐BUS
Figure 3. Figure 4.
MC74AC652, MC74ACT652
www.onsemi.com
2
PIN ASSIGNMENT
PIN FUNCTION
A
0
−A
7
Data Register A Inputs
Data Register A Outputs
B
0
−B
7
Data Register B Inputs
Data Register B Outputs
CAB, CBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
GAB, GBA Output Enable Inputs
Figure 6. Logic Symbol
Figure 7. Logic Diagram
B
0
B
1
B
2
B
3
B
4
B
5
A
0
A
1
A
2
A
3
A
4
A
5
A
6
B
6
B
7
A
7
CAB
SAB
GAB
CBA
SBA
GBA
D
0
C
0
D
0
C
0
CAB
SBA
CBA
SAB
GABGBA
B
0
A
0
1 OF 8 CHANNELS
TO 7 OTHER CHANNELS
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 5. Pinout: 24−Lead Plastic Package
(Top View)
2324 22 21 20 19 18
21 34567
V
CC
17
8
16
9
15
10
CBA SBA GBA
B
0
B
1
B
2
B
3
B
4
B
5
CAB SAB GAB A
0
A
1
A
2
A
3
A
4
A
5
A
6
14
11
13
12
B
6
B
7
A
7
GND
MC74AC652, MC74ACT652
www.onsemi.com
3
FUNCTION TABLE
Inputs Data I/O*
Operation or Function
GAB GBA CAB CBA SAB SBA A
0
− A
7
B
0
− B
7
L H H or L H or L X X
Input Input
Isolation
L H ⇑ ⇑ X X Store A and B Data
X H ⇑ H or L X X Input Unspecified* Store A, Hold B
H H ⇑ ⇑ X** X Input Output Store A in Both Registers
L X H or L ⇑ X X Unspecified* Input Hold A, Store B
L L ⇑ ⇑ X X** Output Input Store B in Both Registers
L L X X X L
Output Input
Real-Time B Data to A Bus
L L X H or L X H Stored B Data to A Bus
H H X X L X
Input Output
Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output
Stored A Data to B Bus and
Stored B Data to A Bus
*The data output functions may be enabled or disabled by various signals at the GBA and GAB inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
**Select control = L: clocks can occur simultaneously.
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; ⇑ = LOW-to-HIGH Transition
P1-P3P4-P6P7-P9P10-P10

MC74ACT652NG

Mfr. #:
Buy MC74ACT652NG
Manufacturer:
ON Semiconductor
Description:
Bus Transceivers Octal Transceiver Non-Inverting
Lifecycle:
New from this manufacturer.
Delivery:
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