5/16
M27C256B
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V ± 5% or 5V ± 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V ± 5% or 5V ± 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Symbol Parameter Test Condition Min Max Unit
I
LI
Input Leakage Current 0V ≤
V
IN
≤ V
CC
±10 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±10 µA
I
CC
Supply Current
E
= V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
30 mA
I
CC1
Supply Current (Standby) TTL
E
= V
IH
1mA
I
CC2
Supply Current (Standby) CMOS
E
> V
CC
– 0.2V
100 µA
I
PP
Program Current
V
PP
= V
CC
100 µA
V
IL
Input Low Voltage –0.3 0.8 V
V
IH
(2)
Input High Voltage 2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4 V
V
OH
Output High Voltage TTL
I
OH
= –1mA
3.6 V
Output High Voltage CMOS
I
OH
= –100µA V
CC
– 0.7V
V
Symbol Alt Parameter Test Condition
M27C256B
Unit
-45
(3)
-60 -70 -80
Min Max Min Max Min Max Min Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E
= V
IL
, G = V
IL
45 60 70 80 ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G
= V
IL
45 60 70 80 ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E
= V
IL
25 30 35 40 ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G
= V
IL
025030030030ns
t
GHQZ
(2)
t
DF
Output Enable High
to Output Hi-Z
E
= V
IL
025030030030ns
t
AXQX
t
OH
Address Transition to
Output Transition
E
= V
IL
, G = V
IL
0000ns
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E
should be decoded and used as the prima-
ry device selecting function, while G
should be
made a common connection to all devices in the
array and connected to the READ
line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is desired from a particular memory de-
vice.
