852911I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 21, 20164
TABLE 4D. HSTL DC CHARACTERISTICS, V
DD
= 3.3V±0.3V, V
DDO
= 1.6V TO 3.6V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
HSTL_CLK V
IN
= V
DD
= 3.6V 150 µA
nHSTL_CLK V
IN
= V
DD
= 3.6V 150 µA
I
IL
Input Low Current
HSTL_CLK V
IN
= 0V, V
DD
= 3.6V -5 µA
nHSTL_CLK V
IN
= 0V, V
DD
= 3.6V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3V
V
CMR
Common Mode Input Voltage; NOTE
1, 2
0.5V
DD
- 0.85 V
V
OH
Output High Voltage; NOTE 3 1.01.4V
V
OL
Output Low Voltage; NOTE 3 0 0.4V
V
OX
Output Crossover Voltage; NOTE 4 40 60 %
V
SWING
Peak-to-Peak Output Voltage Swing 0.61.1V
NOTE 1: For single ended applications, the maximum input voltage for HSTL_CLK and nHSTL_CLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
NOTE 3: Outputs terminated with 50Ω to ground.
NOTE 4: Defi ned with respect to output voltage swing at a given condition.
TABLE 5. AC CHARACTERISTICS, V
DD
= 3.3V±0.3V, V
DDO
= 1.6V TO 3.6V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 500 MHz
t
PD
Propagation Delay; NOTE 1 1.31.51.7ns
tsk(o) Output Skew; NOTE 2, 4 100 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 300 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 600 ps
odc Output Duty Cycle 47 53 %
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
Measured from V
DD
/2 to the output differential crossing point for single ended input levels.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
852911I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 21, 20165
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V CORE/1.6V TO 3.6V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
852911I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 21, 20166
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.

852911AVILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 9 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
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