© 1999 Fairchild Semiconductor Corporation DS009973 www.fairchildsemi.com
November 1988
Revised October 1999
74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE
) inputs.
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
Features
■ I
CC
and I
OZ
reduced by 50%
■ Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to 74AC373 and 74ACT373
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ 74ACT573 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74AC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs