© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 9
1 Publication Order Number:
MC100EL38/D
MC100EL38
5V ECL ÷2, ÷4/6 Clock
Generation Chip
Description
The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single-ended ECL or, if positive power supplies
are used, PECL input signal.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The common enable (EN
) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL38s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EL38, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2 and
the ÷4/6 outputs of a single device.
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• ESD Protection:
♦ 2 kV Human Body Model
♦ 100 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
♦ V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
• NECL Mode Operating Range:
♦ V
CC
= 0 V with V
EE
= −4.2 V to −5.7 V
• Internal 75 kW Input Pulldown Resistors on CLK, EN,
MR, and DIVSEL
• Q Output will Default LOW with Inputs Open or at
V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: 3 (Pb-Free)
♦ For Additional Information, see Application Note
AND8003/D
• Flammability Rating:
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 388 devices
• These Devices are Pb-Free, Halogen Free and are
RoHS Compliant
www.onsemi.com
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
SOIC−20 WB
DW SUFFIX
CASE 751D−05
20
1
100EL38
AWLYYWWG
*For additional marking information, refer to
Application Note AND8002/D
.
ORDERING INFORMATION
Device Package Shipping
†
MC100EL38DWR2G SOIC−20 WB
(Pb-Free)
1000/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
