9397 750 13811 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 November 2004 13 of 20
Philips Semiconductors
74HC283
4-bit binary full adder with fast carry
the second stage on S3. As long as A3 and B3 are the same, HIGH or LOW, they do not
influence S3. Similarly, when A3 and B3 are the same, the carry into the third stage does
not influence the carry out of the third stage.
Figure 10 shows a method of implementing a 5-input encoder, where the inputs are
equally weighted. The outputs S1, S2 and S3 produce a binary number equal to the
number inputs (I1 to I5) that are HIGH.
Figure 11 shows a method of implementing a 5-input majority gate. When three or more
inputs (I1 to I5) are HIGH, the output M5 is HIGH.
Fig 8. 3-bit adder Fig 9. 2-bit and 1-bit adder
Fig 10. 5-input encoder Fig 11. 5-input majority gate
001aab900
S4
S3
S2
S1
C3
L
B4
A4
B3
COUT
CIN
A3
B2
A2
B1
A1
001aab901
S4
S3
S2
S1
S1
S2
C2
S10
C1
CIN
B4
A4
B3
COUT
CIN
C10
A3
A10
B2
A2
A2
B1
B1
B2
A1
A1
B10
001aab902
S4
S3
S2
S1
B4
A4
B3
COUT
CIN
I3
A3
I4
B2
A2
L
B1
I2
A1
I1
I5
001aab903
S4
S3
S2
S1
B4
A4
B3
COUT
CIN
I3
A3
I4
M5
B2
A2
B1
I2
A1
I1
I5