24C32A, 24C64A
Figure 8: SCL and SDA Bus Timing
LOW
HIGH
t
t
t
LOW
t
t
F R
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU,STA
t
SU.STO
t
DH
t
BUF
t
AA
SCL
SDA IN
SDA OUT
AC CHARACTERISTICS
1.8V 2.5-5.0 V
Symbol
Parameter
Min Max Min Max
Unit
f
SCL
Clock frequency, SCL 400 800 kHz
t
LOW
Clock pulse width low 1.3 1.2 µs
t
HIGH
Clock pulse width high
0.6 0.6 µs
t
I
Noise suppression
time
(1)
180 120 ns
t
AA
Clock low to data out
valid
0.3 0.9 0.2 0.7 µs
t
BUF
Time the bus must be
free before a new
transmission can start
(1)
1.3 1.2 µs
t
HD.STA
START hold time 0.6 0.6 µs
t
SU.STA
START set-up time 0.6 0.6 µs
t
HD.DAT
Data in hold time 0 0 µs
t
SU.DAT
Data in set-up time 100 100 ns
t
R
Input rise time
(1)
0.3 0.3 µs
t
F
Input fall time
(1)
300 300 ns
t
SU.STO
STOP set-up time 0.6 0.6 µs
t
DH
Date out hold time 200 50 ns
t
WR
Write cycle time 5 5 ms
Endurance
(1)
25
o
C, Page Mode, 3.3V 1,000,000
Write
Cycles
Notes: 1. This Parameter is expected by characterization but are not fully screened by test.
2. AC Measurement conditions:
R
L
(Connects to Vcc): 1.3KΩ
Input Pulse Voltages: 0.3Vcc to 0.7Vcc
Input and output timing reference Voltages: 0.5Vcc
DS3005J-page8 © 2009 Fremont Micro Devices Inc.
