CS8321YT3G

CS8321
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4
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ±20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
CALCULATING POWER DISSIPATION
IN A SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 5) is:
P
D(max)
+
(
V
IN(max)
* V
OUT(min)
)
I
OUT(max)
) V
IN(max)
I
Q
(1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
qJA
can be calculated:
R
qJA
+
150°C * T
A
P
D
(2)
The value of R
qJA
can then be compared with those in the
package section of the data sheet. Those packages with
R
qJA
s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Figure 5. Single Output Regulator with Key
Performance Parameters Labeled
CS8321
V
IN
V
OUT
I
IN
I
OUT
I
Q
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
qJA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(3)
where:
R
qJC
= the junctiontocase thermal resistance,
R
qCS
= the casetoheatsink thermal resistance, and
R
qSA
= the heatsinktoambient thermal resistance.
R
qJC
appears in the package section of the data sheet. Like
R
qJA
, it too is a function of package type. R
qCS
and R
qSA
are
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers.
CS8321
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5
PACKAGE DIMENSIONS
TO2203
T SUFFIX
CASE 221A08
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
A
K
L
G
D
N
H
Q
F
123
4
T
SEATING
PLANE
S
R
J
U
T
C
3 PL
B
Y
M
B
M
0.25 (0.010) Y
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.560 0.625 14.23 15.87
B 0.380 0.420 9.66 10.66
C 0.140 0.190 3.56 4.82
D 0.025 0.035 0.64 0.89
F 0.139 0.155 3.53 3.93
G 0.100 BSC 2.54 BSC
H −−− 0.280 −−− 7.11
J 0.012 0.045 0.31 1.14
K 0.500 0.580 12.70 14.73
L 0.045 0.060 1.15 1.52
N 0.200 BSC 5.08 BSC
Q 0.100 0.135 2.54 3.42
R 0.080 0.115 2.04 2.92
S 0.020 0.055 0.51 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V
V 0.045 −−− 1.15 −−−
PACKAGE THERMAL DATA
Parameter TO2203 D
2
PAK3 Unit
R
q
JC
Typical 3.5 1.0* °C/W
R
q
JA
Typical 50 1050† °C/W
*Depending on die area.
†Depending on thermal properties of substrate. R
q
JA
= R
q
JC
+ R
q
CA
.
CS8321
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6
PACKAGE DIMENSIONS
D
2
PAK3
DP SUFFIX
CASE 418AB01
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. PACKAGE OUTLINE EXCLUSIVE OF MOLD
FLASH AND METAL BURRS.
4. PACKAGE OUTLINE INCLUSIVE OF
PLATING THICKNESS.
5. FOOT LENGTH MEASURED AT INTERCEPT
POINT BETWEEN DATUM A AND LEAD
SURFACE.
A
C
B
S
K
E
M
P
N
D
G
H
W
R
A
U
V
TERMINAL 4
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.396 0.406 10.05 10.31
B 0.330 0.340 8.38 8.64
C 0.170 0.180 4.31 4.57
D 0.026 0.036 0.66 0.91
E 0.045 0.055 1.14 1.40
G 0.100 REF 2.54 REF
H 0.580 0.620 14.73 15.75
K 0.055 0.066 1.40 1.68
L 0.000 0.010 0.00 0.25
M 0.098 0.108 2.49 2.74
N 0.017 0.023 0.43 0.58
P 0.090 0.110 2.29 2.79
R 0 8
S 0.095 0.105 2.41 2.67
U 0.30 REF 7.62 REF
V 0.305 REF 7.75 REF
W 0.010 0.25
°°0 8 °°
L
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CS8321YT3G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG LINEAR 5V 150MA TO220AB
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