Philips Semiconductors Product data
74F862
Bus transceiver, inverting (3-State)
2
2004 Jan 23
FEATURES
• Provide high performance bus interface buffering for wide
data/address paths or buses carrying parity
• High impedance NPN base inputs for reduced loading (20 µA in
HIGH and LOW states)
• I
IL
is 20 µA for minimum bus loading
• Buffered control inputs for light loading, or increased fan-in as
required with MOS microprocessors
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim dual In-line (DIP) 300 mil package
• Broadside pinout
• Outputs sink 64 mA
DESCRIPTION
The 74F862 bus transceiver provides a high performance inverting
bus interface for wide data/address paths of buses carrying parity.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F862 6.0 ns 150 mA
ORDERING INFORMATION
COMMERCIAL RANGE: V
CC
= 5 V
±
10%; T
amb
= 0
°
C to +70
°
C
Type number
Package
Name Description Version
N74F862N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1
N74F862D (see Note 1) SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
NOTE:
1. Thermal mounting techniques are recommended. See SMD Process Applications for a discussion of thermal considerations for surface
mounted devices.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A9 Data transmit inputs 1.0/0.033 20 µA / 20 µA
B0 – B9 Data receive inputs 1.0/0.033 20 µA / 20 µA
OEBA Transmit output enable input 1.0/0.033 20 µA / 20 µA
OEAB Receive output enable input 1.0/0.033 20 µA / 20 µA
NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the HiGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
18
24
OEAB
B0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
V
CC
13
23
22
21
20
19
17
16
15
14
TOP VIEW
74F862
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
SF00521
