CYV270M0101EQ-SXC Datasheet CYV270M0101EQ-SXC | P1-P3

CYV270M0101EQ

Adaptive Video Cable Equalizer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06830 Rev. *B Revised October 25, 2007

Features

■ Adaptive cable equalization

■ SMPTE 259M compliant

■ Supports DVB-ASI at 270 Mbps

■ Multi standard operation from 143 Mbps to 360 Mbps

■ Cable length indicator for SD-SDI data rates

■ Maximum cable length adjustment for SD-SDI data rates

■ Carrier detect and mute functionality for SD-SDI data rates

■ Equalizer bypass mode

■ Seamless connection with HOTLink II™ family and HOTLink

receiver

■ Equalizes up to 350m of Canare L-5CFB and Belden 1694A

coaxial cable at 270 Mbps

■ Low power 160 mW at 3.3V

■ Single 3.3V supply

■ 16-pin SOIC

■ 0.18 μm CMOS technology

■ Pb-free and RoHS compliant

■ Uses Cypress CLEANLink™ technology

■ Pin compatible to existing equalizer devices

Functional Description

The CYV270M0101EQ is an adaptive video cable equalizer

designed to equalize and restore signals received over 75Ω

coaxial cable. The equalizer meets SMPTE 259M data rates and

is optimized for performance at 270 Mbps. The

CYV270M0101EQ is optimized to equalize up to 350m of

Canare L-5CFB and Belden 1694A coaxial cable at 270 Mbps.

The CYV270M0101EQ connects seamlessly to the HOTLink II

family of transceivers and HOTLink receivers.

The CYV270M0101EQ has DC restoration for compensation of

the DC content of the SMPTE pathological patterns. A cable

length indicator (CLI) provides an indication of the cable length

equalized at SD-SDI data rates. The maximum cable length

adjust (MCLADJ) sets the approximate maximum cable length to

equalize. The CYV270M0101EQ differential serial outputs

(SDO, SDO

) mute when the approximate cable length set by

MCLADJ is reached. CD

/MUTE is a bidirectional pin that

provides an indication of the signal present at the equalizer

inputs. It also controls muting the outputs of the equalizer.

Power consumption is typically 160 mW at 3.3V.

Serial Links

Copper Cable

CYV270M0101EQ

Connections

Equalizer System Connection Diagram

Cable

Driver

HOTLink II

Serializer

HOTLink II

Deserializer

Adaptive

Cable

Equalizer

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CYV270M0101EQ

Document Number: 001-06830 Rev. *B Page 2 of 10

Pinouts

Figure 1. Pin Diagram - 16 Pin SOIC (Top View)

Equalizer Block Diagram

CYV270M0101EQ Adaptive Video Cable Equalizer Block Diagram

Differential Output

Cable Length Analog

Adjustor and Mute

Threshold Block

Carrier Detect and

Mute Control Block

DC Restore

Equalizer

MUTE

BYPASS

SDO, SDO

SDI, SDI

MCLADJ

CYV270M0101EQ

VCC

GND

SDO

GND

MCLADJ

BYPASS

CD/MUTE

VCC

GND

SDI

GND

AGC+

AGC-

CLI

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CYV270M0101EQ

Document Number: 001-06830 Rev. *B Page 3 of 10

Table 1. Pin Descriptions - CYV270M0101EQ Single Channel Cable Equalizer

Name IO Characteristics Signal Description

Control Signals

CLI Analog Output Cable Length Indicator. CLI provides an analog voltage proportional to the equalized

cable length.

CD/MUTE LVTTL IO Carrier Detect/Mute Indicator.

Output:

When the incoming data stream is present and the cable length does not exceed that set

by MCLADJ, the CD/MUTE outputs a voltage less than 0.8V.

When the incoming data stream is not present or the cable length exceeds that set by

MCLADJ, the CD

/MUTE outputs a voltage greater than 2.8V.

Input:

When the CD

/MUTE pin is set LOW, the equalizer’s differential serial outputs are not muted.

When the CD

/MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted.

MCLADJ Analog Input Maximum Cable Length Adjust. The maximum equalized cable length is set by the

voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is

reached, CD is driven high and the differential output is muted.

If MCLADJ functionality is not needed, this pin should be left floating or tied to ground to

allow maximum equalized cable length.

BYPASS LVTTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s

differential serial inputs (SDI, SDI

) is routed to the equalizer’s differential serial outputs

(SDO, SDO

) without equalizing.

When BYPASS is set LOW, the incoming video data stream is equalized and presented at

the equalizer‘s serial differential outputs (SDO, SDO

In equalizer bypass mode, CD/MUTE is not functional.

AGC± Analog Automatic Gain Control. Place a capacitor of 1 μF between the AGC± pins.

SDO, SDO Differential

Output

Differential Serial Outputs. The equalized serial video data stream is presented at the

SDO/SDO

differential serial CML output.

SDI, SDI Differential

Input

Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial video

data stream over 75Ω coaxial cable.

Power

VCC Power +3.3V Power.

GND Gnd Connect to Ground.

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P1-P3 P4-P6 P7-P9 P10-P10

CYV270M0101EQ-SXC

Mfr. #:

Buy CYV270M0101EQ-SXC

Manufacturer:

Cypress Semiconductor

Description:

Equalizers Std Definition Video Equalizr COM

Lifecycle:

New from this manufacturer.

Delivery:

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CYV270M0101EQ-SXC