PCA9509 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 4 November 2014 4 of 24
NXP Semiconductors
PCA9509
Level translating I
2
C-bus/SMBus repeater
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] Port A and port B can be used for either SCL or SDA.
Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for SO8
Fig 4. Pin configuration for XQFN8
PCA9509DP
V
CC(A)
V
CC(B)
A1 B1
A2 B2
GND EN
002aac126
1
2
3
4
6
5
8
7
PCA9509D
V
CC(A)
V
CC(B)
A1 B1
A2
B2
GND EN
002aac127
1
2
3
4
6
5
8
7
DDD
3&$*0
7UDQVSDUHQWWRSYLHZ
WHUPLQDO
LQGH[DUHD
$
$
9
&&$
%
(1
%
*1' 9
&&%
Table 3. Pin description
Symbol Pin Description
V
CC(A)
1 port A power supply
A1
[1]
2 port A (lower voltage side)
A2
[1]
3 port A (lower voltage side)
GND 4 ground (0 V)
EN 5 enable input (active HIGH)
B2
[1]
6 port B (SMBus/I
2
C-bus side)
B1
[1]
7 port B (SMBus/I
2
C-bus side)
V
CC(B)
8 port B power supply
PCA9509 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 4 November 2014 5 of 24
NXP Semiconductors
PCA9509
Level translating I
2
C-bus/SMBus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9509.
The PCA9509 enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 1.35 V
without degradation of system performance. The PCA9509 contains 2 bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage and 3.3 V SMBus or 5 V I
2
C-bus. The port B I/Os are
over-voltage tolerant to 5.5 V even when the device is unpowered.
The PCA9509 includes a power-up circuit that keeps the output drivers turned off until
V
CC(B)
is above 2.5 V and the V
CC(A)
is above 0.8 V. V
CC(B)
and V
CC(A)
can be applied in
any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on
port A (below approximately 0.15 V) turns on the corresponding port B driver (either SDA
or SCL) and drives port B down to about 0 V. When port A rises above approximately
0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the
pin HIGH. When port B falls first and goes below 0.3V
CC(B)
, the port A driver is turned on
and port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless the
port A voltage goes below V
ILc
. If the port A low voltage goes below V
ILc
, the port B
pull-down driver is enabled until port A rises above approximately 0.15 V (V
ILc
), then
port B, if not externally driven LOW, continues to rise being pulled up by the external
pull-up resistor.
Remark: Ground offset between the PCA9509 ground and the ground of devices on
port A of the PCA9509 must be avoided.
The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of
sinking 3 mA of current at 0.4 V has an output resistance of 133 or less (R = E / I). Such
a driver shares enough current with the port A output pull-down of the PCA9509 to be
seen as a LOW as long as the ground offset is zero. If the ground offset is greater than
0 V, then the driver resistance must be less. Since V
ILc
can be as low as 90 mV at cold
temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 50 mV.
Bus repeaters that use an output offset are not interoperable with the port A of the
PCA9509 as their output LOW levels will not be recognized by the PCA9509 as a LOW. If
the PCA9509 is placed in an application where the V
IL
of port A of the PCA9509 does not
go below its V
ILc
, it pulls port B LOW initially when port A input transitions LOW, but the
port B returns HIGH, so it does not reproduce the port A input on port B. Such applications
should be avoided.
Port B is interoperable with all I
2
C-bus slaves, masters and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
2
C-bus operation because disabling during
a bus operation hangs the bus and enabling part way through a bus cycle could confuse
the I
2
C-bus parts being enabled.
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
PCA9509 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 4 November 2014 6 of 24
NXP Semiconductors
PCA9509
Level translating I
2
C-bus/SMBus repeater
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. Port B is
designed to work with Standard-mode and Fast-mode I
2
C-bus devices in addition to
SMBus devices. Standard-mode I
2
C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I
2
C-bus system where Standard-mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the CPU is running on a 1.35 V
I
2
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
When port B of the PCA9509 is pulled LOW by a driver on the I
2
C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3V
CC(B)
and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9509 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to Figure 6
and Figure 7. If the bus master in
Figure 5
were to write to the slave through the PCA9509, waveforms shown in Figure 6
would be observed on the B bus. This looks like a normal I
2
C-bus transmission.
On the A bus side of the PCA9509, the clock and data lines are driven by the master and
swing nearly to ground. After the eighth clock pulse, the slave replies with an ACK that
causes a LOW on the A side equal to the V
OL
of the PCA9509, which the master
recognizes as a LOW. It is important to note that any arbitration or clock stretching events
require that the LOW level on the A bus side at the input of the PCA9509 (V
IL
) is below
V
ILc
to be recognized by the PCA9509 and then transmitted to the B bus side.
Fig 5. Typical application
002aac128
V
CC(B)
V
CC(A)
PCA9509
A1 B1
A2 B2
EN
10 kΩ
10 kΩ
SDA
SCL
MASTER
CPU
SLAVE
400 kHz
SDA
SCL
bus A bus B
3.3 V
1.35 V
10 kΩ
1.35 V

PCA9509DP,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Signal Buffers, Repeaters I2C LV LVL TRANSLATR
Lifecycle:
New from this manufacturer.
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