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8SLVD1204-33NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DATA SHEET
2:4, LVDS Output Fanout Buffer 8SLVD1204-33
8SLVD1204-33 REVSION B 03/11/15 1 ©2015 Integrated Device Technology, Inc.
General Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204-33
is characterized to operate from a 3.3V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204-33 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 310ps (maximum)
• Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
10kHz - 20MHz: 100fs (maximum)
• Full 3.3V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
PCLK1
nPCLK1
VDD
Pullup/Pulldown
Pulldown
SEL
Pullup/Pulldown
0
1
PCLK0
nPCLK0
VDD
GND
Pullup/Pulldown
Pulldown
VDD
GND
Reference
Voltage
Generator
VREF
GND
GND GND
16-pin, 3mm x 3mm VFQFN Package
8XXXXXX
nQ3
Q3
nQ2
Q2
8SLVD1204-33
12
11 10 9
nQ1
Q1
Q0
nQ0
1
2
34
GND
SEL
PCLK1
14
15
16
13
nPCLK1
8
7
6
5
V
DD
PCLK0
nPCLK0
V
REF
8SLVD1204-33 DATA SHEET
2:4, LVDS OUTPUT FANOUT BUFFER 2 REVSION B 03/11/15
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. SEL Input Selection Function Table
NOTE: SEL is an asynchronous control.
Number Name Type Description
1GNDPower
Power supply ground.
2 SEL Input
Pullup/
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
3 PCLK1 Input Pulldown
Non-inverting differential clock/data input.
4 nPCLK1 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
5V
DD
Power
Power supply pin.
6 PCLK0 Input Pulldown
Non-inverting differential clock/data input.
7 nPCLK0 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
8V
REF
Output Bias voltage reference for the PCLKx, nPCLKx inputs.
9, 10 Q0, nQ0 Output
Differential output pair 0. LVDS interface levels.
11, 12 Q1, nQ1 Output
Differential output pair 1. LVDS interface levels.
13, 14 Q2, nQ2 Output
Differential output pair 2. LVDS interface levels.
15, 16 Q3, nQ3 Output
Differential output pair 3. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
Input
OperationSEL
0 PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
Open (default)
Internally set to V
DD
/2.
Input buffers are disabled and outputs are static.
REVSION B 03/11/15 3 2:4, LVDS OUTPUT FANOUT BUFFER
8SLVD1204-33 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Electrical Characteristics
Table 4A. Power Supply Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
10mA
15mA
V
REF
Current (Sink/Source), I
REF
±2mA
Maximum Junction Temperature, T
J,MAX
125°C
Storage Temperature, T
STG
-65C to 150C
ESD - Human Body Model, NOTE 1 2000V
ESD - Charged Device Model, NOTE 1 1500V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current
SEL = 0 or 1; f
REF
= 100MHz; Q0 to Q3
terminated 100between nQx, Qx
86 100 mA
SEL = 0 or 1; f
REF
= 800MHz; Q0 to Q3
terminated 100between nQx, Qx
86 100 mA
SEL = 0 or 1; f
REF
= 2GHz; Q0 to Q3
terminated 100between nQx, Qx
86 100 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage SEL 0.7 * V
DD
V
DD
+ 0.3 V
V
IL
Input Low Voltage SEL -0.3 0.2 * V
DD
V
I
IH
Input High Current SEL V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current SEL V
DD
= 3.465V, V
IN
= 0V -150 µA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8SLVD1204-33NLGI

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Description:
Clock Drivers & Distribution LVDS Fanout Buffer
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