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8SLVD1204-33NLGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
8SLVD1204-33 DATA SHEET
2:4, LVDS OUTPUT FANOUT BUFFER 4 REVSION B 03/11/15
Table 4C. Differential Input DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Table 4D. LVDS DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High
Current
PCLK0,
nPCLK1
PCLK1,
nPCLK1
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low
Current
PCLK0,
PCLK1
V
DD
= 3.465V, V
IN
= 0V -10 µA
nPCLK0,
nPCLK1
V
DD
= 3.465V, V
IN
= 0V -150 µA
V
REF
Reference Voltage
for Input Bias
I
REF
= ±1mA V
DD
– 1.50 V
DD
– 1.35 V
DD
– 1.15 V
V
PP
Peak-to-Peak Voltage;
NOTE 1
f
REF
< 1.5 GHz 0.1 1.5 V
f
REF
1.5 GHz 0.2 1.5 V
V
CMR
Common Mode Input
Voltage; NOTES 1, 2
1.0 V
DD
– 0.6 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 247 454 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.15 1.45 V
V
OS
V
OS
Magnitude Change 50 mV
REVSION B 03/11/15 5 2:4, LVDS OUTPUT FANOUT BUFFER
8SLVD1204-33 DATA SHEET
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input
Frequency
PCLK[0:1],
nPCLK[0:1]
2GHz
V/t
Input
Edge Rate
PCLK[0:1],
nPCLK[0:1]
1.5 V/ns
t
PD
Propagation Delay;
NOTE 1
PCLK[0:1], nPCLK[0:1] to any Qx, nQx
for V
PP
= 0.1V or 0.3V
120 215 310 ps
tsk(o)
Output Skew;
NOTES 2, 3
20 ps
tsk(i) Input Skew; NOTE 3 20 ps
tsk(p) Pulse Skew f
REF
= 100MHz 15 ps
tsk(pp)
Part-to-Part Skew;
NOTES 3, 4
230 ps
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
139 190 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
95 140 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
95 140 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
90 130 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
67 100 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
67 100 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
94 140 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
70 105 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
70 105 fs
t
R
/ t
F
Output Rise/ Fall Time
20% to 80%
outputs loaded with 100
40 250 ps
MUX
ISOLATION
Mux Isolation; NOTE 5 f
REF
= 100MHz 74 dB
8SLVD1204-33 DATA SHEET
2:4, LVDS OUTPUT FANOUT BUFFER 6 REVSION B 03/11/15
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
SSB Phase Noise (dBc/Hz)
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @ 156.25MHz, V
PP
= 1V,
Integration Range (12kHz to 20MHz) = 67fs (typical)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8SLVD1204-33NLGI8

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Manufacturer:
IDT
Description:
Clock Drivers & Distribution LVDS Fanout Buffer
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