LT3800
6
3800fc
PIN FUNCTIONS
and reverse-current inhibit functions are enabled. When
the pin voltage is above 0.5V, Burst Mode operation is dis-
abled, but reverse-current inhibit operation is maintained.
DC/DC converters operating with reverse-current inhibit
operation (BURST_EN = V
FB
) have a 1mA minimum load
requirement. Reverse-current inhibit is disabled when the
pin voltage is above 2.5V. This pin is typically shorted to
ground to enable Burst Mode operation and reverse-current
inhibit, shorted to V
FB
to disable Burst Mode operation
while enabling reverse-current inhibit, and connected
to V
CC
pin to disable both functions. See Applications
Information section.
V
FB
(Pin 6): Error Amplifi er Inverting Input. The noninvert-
ing input of the error amplifi er is connected to an internal
1.231V reference. Desired converter output voltage (V
OUT
)
is programmed by connecting a resistive divider from the
converter output to the V
FB
pin. Values for the resistor
connected from V
OUT
to V
FB
(R2) and the resistor con-
nected from V
FB
to ground (R1) can be calculated via the
following relationship:
R2 = R1•
V
OUT
1.231
–1
The V
FB
pin input bias current is 25nA, so use of extremely
high value feedback resistors could cause a converter
output that is slightly higher than expected. Bias current
error at the output can be estimated as:
∆V
OUT(BIAS)
= 25nA • R2
V
C
(Pin 7): Error Amplifi er Output. The voltage on the V
C
pin corresponds to the maximum (peak) switch current per
oscillator cycle. The error amplifi er is typically confi gured
as an integrator by connecting an RC network from this
pin to ground. This network creates the dominant pole for
the converter voltage regulation feedback loop. Specifi c
integrator characteristics can be confi gured to optimize
transient response. Connecting a 100pF or greater high
frequency bypass capacitor from this pin to ground is also
recommended. When Burst Mode operation is enabled (see
Pin 5 description), an internal low impedance clamp on the
V
C
pin is set at 100mV below the burst threshold, which
limits the negative excursion of the pin voltage. There-
fore, this pin cannot be pulled low with a low-impedance
source. If the V
C
pin must be externally manipulated, do
so through a 1k series resistance.
SENSE
–
(Pin 8): Negative Input for Current Sense Ampli-
fi er. Sensed inductor current limit set at ±150mV across
SENSE inputs.
SENSE
+
(Pin 9): Positive Input for Current Sense Ampli-
fi er. Sensed inductor current limit set at ±150mV across
SENSE inputs.
PGND (Pin 10): High Current Ground Reference for Syn-
chronous Switch. Current path from pin to negative terminal
of V
CC
decoupling capacitor must not corrupt SGND.
BG (Pin 11): Synchronous Switch Gate Drive Output.
V
CC
(Pin 12): Internal Regulator Output. Most IC func-
tions are powered from this pin. Driving this pin from
an external source reduces V
IN
pin current to 20µA.
This pin is decoupled with a low ESR 1µF capacitor to
PGND. In shutdown mode, this pin sinks 20µA until the
pin voltage is discharged to 0V. See Typical Performance
Characteristics.
NC (Pin 13): No Connection.
SW (Pin 14): Reference for V
BOOST
Supply and High Cur-
rent Return for Bootstrapped Switch.
TG (Pin 15): Bootstrapped Switch Gate Drive Output.
BOOST (Pin 16): Bootstrapped Supply – Maximum Operat-
ing Voltage (Ground Referred) to 75V. This pin is decoupled
with a low ESR 1µF capacitor to pin SW. The voltage on
the decoupling capacitor is refreshed through a rectifi er
from either V
CC
or an external source.
Exposed Package Backside (SGND) (Pin 17): Low Noise
Ground Reference. SGND connection is made through
the exposed lead frame on back of TSSOP package which
must be soldered to the PCB ground.
