OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LT3800IFE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LT3800
16
3800fc
APPLICATIONS INFORMATION
Power MOSFET Selection
External N-channel MOSFET switches are used with the
LT3800. The positive gate-source drive voltage of the
LT3800 for both switches is roughly equivalent to the V
CC
supply voltage, for use of standard threshold MOSFETs.
Selection criteria for the power MOSFETs include the
“ON” resistance (R
DS(ON)
), total gate charge (Q
G
), reverse
transfer capacitance (C
RSS
), maximum drain-source volt-
age (V
DSS
) and maximum current.
The power FETs selected must have a maximum operating
V
DSS
exceeding the maximum V
IN
. V
GS
voltage maximum
must exceed the V
CC
supply voltage.
Total gate charge (Q
G
) is used to determine the FET gate
drive currents required. Q
G
increases with applied gate
voltage, so the Q
G
for the maximum applied gate voltage
must be used. A graph of Q
G
vs. V
GS
is typically provided
in MOSFET data sheets.
In a confi guration where the LT3800 linear regulator is
providing V
CC
and V
BOOST
currents, the V
CC
8V output
voltage can be used to determine Q
G
. Required drive cur-
rent for a given FET follows the simple relation:
I
GATE
= Q
G(8V)
• f
O
Q
G(8V)
is the total FET gate charge for V
GS
= 8V, and f
0
=
operating frequency. If these currents are externally derived
by backdriving V
CC
, use the backfeed voltage to determine
Q
G
. Be aware, however, that even in a backfeed confi gura-
tion, the drive currents for both boosted and synchronous
FETs are still typically supplied by the LT3800 internal V
CC
regulator during start-up. The LT3800 can start using FETs
with a combined Q
G(8V)
up to 180nC.
Once voltage requirements have been determined, R
DS(ON)
can be selected based on allowable power dissipation and
required output current.
In an LT3800 buck converter, the average inductor cur-
rent is equal to the DC load current. The average cur-
rents through the main (bootstrapped) and synchronous
(ground-referred) switches are:
I
MAIN
= (I
LOAD
)(DC)
I
SYNC
= (I
LOAD
)(1 – DC)
The R
DS(ON)
required for a given conduction loss can be
calculated using the relation:
P
LOSS
= I
SWITCH
2
• R
DS(ON)
In high voltage applications (V
IN
> 20V), the main switch
is required to slew very large voltages. MOSFET transition
losses are proportional to V
IN
2
and can become the domi-
nant power loss term in the main switch. This transition
loss takes the form:
P
TR
≈ (k)(V
IN
)
2
(I
SWITCH
)(C
RSS
)(f
O
)
where k is a constant inversely related to the gate drive
current, approximated by k = 2 in LT3800 applications,
and I
SWITCH
is the converter output current. The power
loss terms for the switches are thus:
P
MAIN
= (DC)(I
SWITCH
)
2
(1 + d)(R
DS(ON)
) +
2(V
IN
)
2
(I
SWITCH
)(C
RSS
)(f
O
)
P
SYNC
= (1 – DC)(I
SWITCH
)
2
(1 + d)(R
DS(ON)
)
The (1 + d) term in the above relations is the temperature
dependency of R
DS(ON)
, typically given in the form of a
normalized R
DS(ON)
vs Temperature curve in a MOSFET
data sheet.
The C
RSS
term is typically smaller for higher voltage FETs,
and it is often advantageous to use a FET with a higher
V
DS
rating to minimize transition losses at the expense of
additional R
DS(ON)
losses.
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT3800, causing a negative voltage
in excess of the Absolute Maximum Rating to be imposed
on that pin. Connection of a catch Schottky diode from
this pin to ground will eliminate this effect. A 1A current
rating is typically suffi cient for the diode.
Input Capacitor Selection
The large currents typical of LT3800 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
buck operation, the source current of the main switch
MOSFET is a square wave of duty cycle V
OUT
/V
IN
. Most
of this current is provided by the input bypass capacitor.
LT3800
17
3800fc
APPLICATIONS INFORMATION
To prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
I
RMS
=
I
MAX
V
OUT
V
IN
–V
OUT
()
()
1
2
V
IN
which peaks at a 50% duty cycle, when I
RMS
= I
MAX
/2.
The bulk capacitance is calculated based on an accept-
able maximum input ripple voltage, ∆V
IN
, which follows
the relation:
C
IN(BULK)
= I
OUT(MAX)
•
V
OUT
V
IN
V
IN
•f
O
∆V is typically on the order of 100mV to 200mV. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit area.
The capacitor voltage rating must be rated greater than
V
IN(MAX)
. The combination of aluminum electrolytic ca-
pacitors and ceramic capacitors is a common approach
to meeting supply input capacitor requirements. Multiple
capacitors are also commonly paralleled to meet size or
height requirements in a design.
Capacitor ripple current ratings are often based on only
2000 hours (three months) lifetime; it is advisable to derate
either the ESR or temperature rating of the capacitor for
increased MTBF of the regulator.
Output Capacitor Selection
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
peak ripple current is equal to that in the inductor (∆I
L
),
typically a fraction of the load current. C
OUT
is selected
to reduce output voltage ripple to a desirable value given
an expected output ripple current. Output ripple (∆V
OUT
)
is approximated by:
∆V
OUT
≈ ∆I
L
(ESR + [(8)(f
O
) • C
OUT
]
–1
)
where f
O
= operating frequency.
∆V
OUT
increases with input voltage, so the maximum
operating input voltage should be used for worst-case
calculations. Multiple capacitors are often paralleled to
meet ESR requirements. Typically, once the ESR require-
ment is satisfi ed, the capacitance is adequate for fi ltering
and has the required RMS current rating. An additional
ceramic capacitor in parallel is commonly used to reduce
the effect of parasitic inductance in the output capacitor,
which reduces high frequency switching noise on the
converter output.
Increasing inductance is an option to reduce ESR require-
ments. For extremely low
∆
V
OUT,
an additional LC fi lter
stage can be added to the output of the supply. Application
Note 44 has information on sizing an additional output
LC fi lter.
Layout Considerations
The LT3800 is typically used in DC/DC converter designs
that involve substantial switching transients. The switch
drivers on the IC are designed to drive large capacitances
and, as such, generate signifi cant transient currents them-
selves. Careful consideration must be made regarding
supply bypass capacitor locations to avoid corrupting the
ground reference used by IC.
Typically, high current paths and transients from the input
supply and any local drive supplies must be kept isolated
from SGND, to which sensitive circuits such as the error
amp reference and the current sense circuits are referred.
Effective grounding can be achieved by considering switch
current in the ground plane, and the return current paths of
each respective bypass capacitor. The V
IN
bypass return,
V
CC
bypass return, and the source of the synchronous
FET carry PGND currents. SGND originates at the negative
terminal of the V
OUT
bypass capacitor, and is the small
signal reference for the LT3800.
Don’t be tempted to run small traces to separate ground
paths. A good ground plane is important as always, but
PGND referred bypass elements must be oriented such
that transient currents in these return paths do not corrupt
the SGND reference.
During the dead-time between switch conduction, the
body diode of the synchronous FET conducts inductor
LT3800
18
3800fc
APPLICATIONS INFORMATION
current. Commutating this diode requires a signifi cant
charge contribution from the main switch. At the instant
the body diode commutates, a current discontinuity is
created and parasitic inductance causes the switch node
to fl y up in response to this discontinuity. High cur-
rents and excessive parasitic inductance can generate
extremely fast dV/dt rise times. This phenomenon can
cause avalanche breakdown in the synchronous FET
body diode, signifi cant inductive overshoot on the switch
node, and shoot-through currents via parasitic turn-on of
the synchronous FET. Layout practices and component
orientations that minimize parasitic inductance on this
node is critical for reducing these effects.
Ringing waveforms in a converter circuit can lead to device
failure, excessive EMI, or instability. In many cases, you
can damp a ringing waveform with a series RC network
across the offending device. In LT3800 applications, any
ringing will typically occur on the switch node, which
can usually be reduced by placing a snubber across the
synchronous FET. Use of a snubber network, however,
should be considered a last resort. Effective layout practices
typically reduce ringing and overshoot, and will eliminate
the need for such solutions.
Effective grounding techniques are critical for successful
DC/DC converter layouts. Orient power path components
such that current paths in the ground plane do not cross
through signal ground areas. Signal ground refers to the
Exposed Pad on the backside of the LT3800 IC. SGND
is referenced to the (–) terminal of the V
OUT
decoupling
capacitor and is used as the converter voltage feedback
reference. Power ground currents are controlled on the
LT3800 via the PGND pin, and this ground references
the high current synchronous switch drive components,
as well as the local V
CC
supply. It is important to keep
PGND and SGND voltages consistent with each other, so
separating these grounds with thin traces is not recom-
mended. When the synchronous FET is turned on, gate
drive surge currents return to the LT3800 PGND pin from
the FET source. The BOOST supply refresh surge currents
also return through this same path. The synchronous FET
must be oriented such that these PGND return currents do
not corrupt the SGND reference. Problems caused by the
PGND return path are generally recognized during heavy
load conditions, and are typically evidenced as multiple
switch pulses occurring during a single 5µs switch cycle.
This behavior indicates that SGND is being corrupted and
grounding should be improved. SGND corruption can
often be eliminated, however, by adding a small capacitor
(100pF-200pF) across the synchronous switch FET from
drain to source.
The high di/dt loop formed by the switch MOSFETs and
the input capacitor (C
IN
) should have short wide traces
to minimize high frequency noise and voltage stress from
inductive ringing. Surface mount components are preferred
to reduce parasitic inductances from component leads.
Connect the drain of the main switch MOSFET directly to
the (+) plate of C
IN
, and connect the source of the syn-
chronous switch MOSFET directly to the (–) terminal of
C
IN
. This capacitor provides the AC current to the switch
MOSFETs. Switch path currents can be controlled by
orienting switch FETs, the switched inductor, and input
and output decoupling capacitors in close proximity to
each other.
Locate the V
CC
and BOOST decoupling capacitors in close
proximity to the IC. These capacitors carry the MOSFET
drivers’ high peak currents. Locate the small-signal
components away from high frequency switching nodes
(BOOST, SW, TG, V
CC
and BG). Small-signal nodes are
oriented on the left side of the LT3800, while high current
switching nodes are oriented on the right side of the IC
to simplify layout. This also helps prevent corruption of
the SGND reference.
Connect the V
FB
pin directly to the feedback resistors
independent of any other nodes, such as the SENSE
–
pin.
The feedback resistors should be connected between the
(+) and (–) terminals of the output capacitor (C
OUT
).
Locate the feedback resistors in close proximity to the
LT3800 to minimize the length of the high impedance
V
FB
node.
The SENSE
–
and SENSE
+
traces should be routed together
and kept as short as possible.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LT3800IFE#PBF

Mfr. #:
Buy LT3800IFE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High-Voltage Sych Step-Down Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet