9
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 2. Writing to Offset Registers
LD WEN WCLK Selection
0 0 Writing to offset registers:
Empty Offset
Full Offset
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
Figure 3. Offset Register Location and Default Values
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (HF) and Programmable Almost-Full Flag (PAF) will
be reset to HIGH after tRSF. The Programmable Almost-Empty Flag (PAE) will
be reset to LOW after tRSF. The Full Flag (FF) will reset to HIGH. The Empty
Flag (EF) will reset to LOW in IDT Standard mode but will reset to HIGH in FWFT
mode. During reset, the output register is initialized to all zeros and the offset
registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF flag is updated on the rising
edge of WCLK.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data and
no new data is loaded into the output register. The data outputs Q0-Qn maintain
the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write
is performed, EF will go HIGH allowing a read to occur. The EF flag is updated
on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW to HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
LOAD (LD)
The IDT72V205/72V215/72V225/72V235/72V245 devices contain two
12-bit offset registers with data on the inputs, or read on the outputs. When the
Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is
written into the Empty Offset register on the first LOW-to-HIGH transition of the
Write Clock (WCLK). When the LD pin and WEN are held LOW then data is
written into the Full Offset register on the second LOW-to-HIGH transition of
WCLK. The third transition of WCLK again writes to the Empty Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the LD pin HIGH, the
FIFO is returned to normal read/write operation. When the LD pin is set LOW,
and WEN is LOW, the next offset register in sequence is written.
EMPTY OFFSET REGISTER
17
11
0
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
FULL OFFSET REGISTER
17
11
0
DEFAULT VALUE
DEFAULT VALUE
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
4294 drw 04
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
