AD7545
–6–
REV. A
V
DD
= +5 volts. However, great care should be taken to ensure
that the +5 V used to power the AD7545 is free from digitally
induced noise.
Temperature Coefficients: The gain temperature coefficient
of the AD7545 has a maximum value of 5 ppm/°C and a typical
value of 2 ppm/°C. This corresponds to worst case gain shifts of
2 LSBs and 0.8 LSBs respectively over a 100°C temperature
range. When trim resistors Rl and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note “Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs,” Publication Number
E630–10–6/81.
SINGLE SUPPLY OPERATION
The ladder termination resistor of the AD7545 (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and V
DD
. OUT1 and
AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow which will damage the device. (The AD7545 is, however,
protected from the SCR latch-up phenomenon prevalent in
many CMOS devices.)
Figure 7 shows the AD7545 connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the V
REF
pin and has a constant output impedance
equal to R. R
FB
is not used in this circuit.
V
O
12
AD7545
1
2
DB11–DB0
OUT1
AGND
3
18
V
DD
+15V
19
V
REF
REFERENCE
VOLTAGE
DGND
15 VOLT CMOS DIGITAL INPUTS
Figure 7. Single Supply Operation Using Voltage
Switching Mode
The loading on the reference voltage source is code dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a V
DD
of 15 volts. If
V
DD
is reduced from 15 V, or the differential voltage between
OUT1 and AGND is increased to more than 2.5 V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
V
DD
. If the output voltage is required to be offset from ground
by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing V
DD
by the amount of the offset.
V
DD
– Volts
+2
+1
–2
0155
DNL – LSB
10
0
–1
Figure 8. Differential Nonlinearity vs. V
DD
for Figure 7
Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.
V
REF
– Volts
0.5
0.0
–2.0
0105
DNL – LSB
–0.5
–1.0
–1.5
Figure 9. Differential Nonlinearity vs. Reference Voltage
for Figure 7 Circuit. V
DD
= 15 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.
The circuits of Figures 4, 5 and 6 can all be converted to single
supply operation by biasing AGND to some voltage between
V
DD
and DGND. Figure 10 shows the twos complement bipolar
circuit of Figure 5 modified to give a range from +2 V to +8 V
about a “pseudo-analog ground” of 5 V. This voltage range
would allow operation from a single V
DD
of +10 V to +15 V.
The AD584 pin-programmable reference fixes AGND at +5 V.
V
IN
is set at +2 V by means of the series resistors R1 and R2.
There is no need to buffer the V
REF
input to the AD7545
with an amplifier because the input impedance of the D/A con-
verter is constant. Note, however, that since the temperature
coefficient of the D/A reference input resistance is typically
–300 ppm/°C; applications that experience wide temperature
variations may require a buffer amplifier to generate the +2.0 V
at the AD7545 V
REF
pin. Other output voltage ranges can be
obtained by changing R4 to shift the zero point and (R1 + R2)
to change the slope, or gain, of the D/A transfer function. V
DD
must be kept at least 5 V above OUT1 to ensure that linearity is
preserved.
