REV. –16–
ADN8830
The gate drive outputs for the PWM amplifier at P1 (Pin 21)
and N1 (Pin 22) have a typical nonoverlap delay of 65 ns.
This is done to ensure that one FET is completely off before
the other FET is turned on, preventing current from shooting
through both simultaneously.
The input capacitance (C
ISS
) of the FET should not exceed 5 nF.
The P1 and N1 outputs from the ADN8830 have a typical output
impedance of 6 Ω. This creates a time constant in combination
with C
ISS
of the external FETs equal to 6 Ω C
ISS
. To ensure
shoot-through does not occur through these FETs, this time
constant should remain less than 30 ns.
The linear output from the ADN8830 uses N2 (Pin 10) and
P2 (Pin 11) to drive the gates of the linear side FETs, shown as
Q3 and Q4 in Figure 1. Local compensation for the linear ampli-
fier is achieved through the gate-to-drain capacitances (C
GD
) of
Q3 and Q4. The value of C
GD
, which can be determined from
the data sheet, is usually referred to as C
RSS
, the reverse transfer
capacitance. The exact C
RSS
value should be determined from a
graph that shows capacitance versus drain-to-source voltage,
using the power supply voltage as the appropriate V
DS
.
To ensure stability of the linear amplifier, the total C
GD
of the
PMOS device, Q3, should be greater than 2.5 nF and the total
C
GD
of the NMOS should be greater than 150 pF. External
capacitance can be added around the FET to increase the effective
C
GD
of the transistor. This is the function of C6 in the typical
application schematic shown in Figure 1. If external capacitance
must be added, it will generally only be required around the
PMOS transistor.
In the event of zero output current through the TEC, there will
be no current flowing through Q3 and Q4. In this condition,
these FETs will not provide any small signal gain and thus no
negative feedback for the linear amplifier. This leaves only a
feedforward signal path through C
GD
, which could cause a
settling problem at OUT B. This is often seen as a small signal
oscillation at OUT B, but only when the TEC is at or very near
zero current.
The remedy for this potential minor instability is to add
capacitance from OUT B to ground. This may need to be deter-
mined empirically, but a good starting point is 1.5 times the
total C
GD
. This is the function of C12 in Figure 1. Note that
while adding more C
GD
around Q3 and Q4 will help to ensure
stability, it could potentially increase instability in the zero current
dead band region, requiring additional capacitance from
OUT B to ground.
Bear in mind that the addition of these capacitors is only
for local stabilization. The stability of the entire TEC appli-
cation may need adjustment, which should be done around the
compensation amplifier. This is covered in the Compensation
Loop section.
There is one additional consideration for selecting both the
linear output FETs; they must have a minimum threshold
voltage (V
T
) of 0.6 V. Lower threshold voltages could cause
shoot-through current in the linear output transistors.
Table V shows the recommended FETs that can be used for the
linear output in the ADN8830 application. Table V includes the
appropriate external gate-to-drain capacitance (external C
GD
)
and snubber capacitor value (C
SNUB
) connected from OUT B to
ground that should be added to ensure local stability. Table VI
shows the recommended PWM output FETs. Although other
transistors can be used, these combinations have been tested
and are proved stable and reliable for typical applications.
Data sheets for these devices can be found at their respective
websites:
Fairchild – www.fairchildsemi.com
Vishay Siliconix – www.vishay.com
International Rectifier – www.irf.com
Calculating Power Dissipation and Efficiency
The total efficiency of the ADN8830 application circuit is simply
the ratio of the output power to the TEC divided by the total
power delivered from the supply. The idea in minimizing power
dissipation is to avoid both drawing additional power and reduc-
ing heat generated from the circuit. The dominant sources
of power dissipation will include resistive losses, gate charge
loss, core loss from the inductor, and the current used by the
ADN8830 itself.
The on-channel resistance of both the linear and PWM output
FETs will affect efficiency primarily at high output currents.
Because the linear amplifier operates in a high gain configuration,
it will be at either ground or V
DD
when significant current is
flowing through the TEC. In this condition, the power dissipation
through the linear output FET will be
PrI
FET LIN DS ON TEC,,
=×
2
(34)
using either the r
DS, ON
for the NMOS or the PMOS depending
on the direction of the current flow. In the typical application
setup in Figure 2, if the TEC is cooling the target object, the
PMOS is sourcing the current. If the TEC is heating the
object, the NMOS will be sinking current.
Table IV. Partial List of Capacitors and Key Specifications
Value (F) ESR (m⍀) Voltage Rating (V) Part Number Manufacturer Website
10 60 6.3 NSP100M6.3D2TR NIC Components www.niccomp.com
22* 35 8 ESRD220M08B Cornell Dubilier www.cornell-dubilier.com
22 35 8 NSP220M8D5TR NIC Components www.niccomp.com
22 35 8 EEFFD0K220R Panasonic www.maco.panasonic.co.jp
47 25 6.3 NSP470M6.3D2TR NIC Components www.niccomp.com
68 18 8 ESRD680M08B Cornell Dubilier www.cornell-dubilier.com
100 95 10 594D107X_010C2T Vishay www.vishay.com
*Recommend capacitor in typical application circuit Figure 1.
D
