EMC1186-2-AC3 Datasheet EMC1186-2-AC3-TR, EMC1186-2-AC3, EMC1186-1-AC3 | P13-P15

Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications

Datasheet

SMSC EMC1186 13 Revision 1.0 (07-11-13)

DATASHEET

Chapter 4 System Management Bus Interface Protocol

4.1 Communications Protocol

The EMC1186 communicates with a host controller, such as an SMSC SIO, through the SMBus. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in

Figure 4.1.

For the first 15ms after power-up the device may not respond to SMBus communications.

4.1.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

4.1.2 SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus Host is reading data from the client device.

The EMC1186-1 SMBus address is hard coded to 1001_100(r/w).

The EMC1186-2 SMBus address is hard coded to 1001_101(r/w).

4.1.3 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.1.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the client device

pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the

Write Byte protocol.

Figure 4.1 SMBus Timing Diagram

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

HIGH

LOW

HD:STA

SU:STO

HD:STA

HD:DAT

SU:DAT

SU:STA

FALL

RISE

Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications

Datasheet

Revision 1.0 (07-11-13) 14 SMSC EMC1186

DATASHEET

The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the

SMBus data line high after the 8th data bit has been sent.

4.1.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic

‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit

and it has been communicating with the SMBus protocol, it will reset its client interface and prepare

to receive further communications.

4.1.6 SMBus Timeout

The EMC1186 supports SMBus Timeout. If the clock line is held low for longer than t

TIMEOUT

, the

device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see

Section 6.11, "Consecutive ALERT Register 22h").

4.1.7 SMBus and I

C Compatibility

The EMC1186 is compatible with SMBus and I

C. The major differences between SMBus and I

devices are highlighted here. For more information, refer to the SMBus 2.0 and I

C specifications. For

information on using the EMC1186 in an I

C system, refer to SMSC AN 14.0 SMSC Dedicated Slave

Devices in I

C Systems.

1. EMC1186 supports I

C fast mode at 400kHz. This covers the SMBus max time of 100kHz.

2. Minimum frequency for SMBus communications is 10kHz.

3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This

timeout functionality is disabled by default in the EMC1186 and can be enabled by writing to the

TIMEOUT bit. I

C does not have a timeout.

4. I

C devices do not support the Alert Response Address functionality (which is optional for SMBus).

Attempting to communicate with the EMC1186 SMBus interface with an invalid slave address or invalid

protocol will result in no response from the device and will not affect its register contents. Stretching

of the SMCLK signal is supported, provided other devices on the SMBus control the timing.

4.2 SMBus Protocols

The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address

as valid protocols as shown below.

All of the below protocols use the convention in Table 4.1.

Table 4.1 Protocol Format

DATA SENT

TO DEVICE

DATA SENT TO

THE HOST

# of bits sent # of bits sent

Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications

Datasheet

SMSC EMC1186 15 Revision 1.0 (07-11-13)

DATASHEET

4.2.1 Write Byte

The Write Byte is used to write one byte of data to the registers, as shown in Table 4.2.

4.2.2 Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3.

4.2.3 Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address

location. No data is transferred during the Send Byte protocol as shown in Table 4.4.

4.2.4 Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address

pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads

of the same register as shown in

Table 4.5.

Table 4.2 Write Byte Protocol

START

SLAVE

ADDRESS WR

ACK

ADDRESS ACK

DATA ACK STOP

1 -> 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1

Table 4.3 Read Byte Protocol

START SLAVE

ADDRESS

WR ACK REGISTER

ADDRESS

ACK START SLAVE

ADDRESS

RD ACK REGISTER

DATA

NACK STOP

1 -> 0 YYYY_

YYY

0 0 XXh 0 1 -> 0 YYYY_

YYY

10 XX 10 -> 1

Table 4.4 Send Byte Protocol

START

SLAVE

ADDRESS WR

ACK

ADDRESS ACK STOP

1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1

Table 4.5 Receive Byte Protocol

START

SLAVE

ADDRESS RD ACK REGISTER DATA NACK STOP

1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P43

EMC1186-2-AC3

Mfr. #:

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Manufacturer:

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Description:

Board Mount Temperature Sensors 1.8V SMBus Dual Temp Sensor

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EMC1186-2-AC3

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