NB4N441MNR2G

© Semiconductor Components Industries, LLC, 2011
April, 2011 Rev. 2
1 Publication Order Number:
NB4N441/D
NB4N441
3.3V Serial Input
MultiProtocol PLL Clock
Synthesizer, Differential
LVPECL Output
Description
The NB4N441 is a precision clock synthesizer which generates a
differential LVPECL clock output frequency from 12.5 MHz to
425 MHz. A Serial Peripheral Interface (SPI) is used to configure the
device to produce one of sixteen popular standard protocol output
frequencies from a single 27 MHz crystal reference. The NB4N441
also has the added feature of allowing application specific output
frequencies from 12.5 MHz to 425 MHz using crystals within the
range of 10 MHz to 28 MHz.
Features
Performs Precision Clock Generation and Synthesis from a Single
27 MHz Crystal Reference
Serial Load Capability for Proprietary Frequencies
Flexible Input Allows for External Clock Reference
Exceeds Bellcore and ITU Jitter Generation Specification
PLL Lock Detect Output
Output Enable
Fully Integrated PhaseLockLoop with Internal Loop Filter
Operating Range: V
CC
= 3.135 V to 3.465 V
Small Footprint 24 Pin QFN
These are PbFree Devices*
27 MHz
XTAL
OSC
B
FB
R
Feedback
Divider
Frequency Control Logic
Serial Load
SDATA
SCLOCK
SLOAD
LOCKED
OUTDIV
B2, 4, 8,
16, 32
CLKOUT
CLKOUT
OE
V
CC
2 V
Figure 1. Simplified Block Diagram
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM*
QFN24
MN SUFFIX
CASE 485L
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
NB4N
441
ALYWG
G
1
24
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
NB4N441
http://onsemi.com
2
CLK/XTAL1
XTAL
OSC
PB
FB
R
Feedback
Divider (MB)
P[4:0] M[9:0] N[3:0]
Frequency Control Logic
Serial Load
SDATA
SCLOCK
SLOAD
LOCKED
OUTDIV (NB)
B2, 4, 8,
16, 32
CLKOUT
CLKOUT
Figure 2. Block Diagram
XTAL2
V
CC
VCC_PLL
PFD
Loop
Filter
VCO
OE
GND
Input
Prescaler
SLOAD
NC
GND
GND
VCC_PLL
NC
V
CC
V
CC
GND
SDATA
Figure 3. QFN24 Lead Pinout (Top View)
SCLOCK
NC
NC
GND
18
12
4
3
5
6
789 1110
2
1
17
16
15
14
13
1924 23 22 2021
Exposed Pad
(EP)
LOCKED
OE
CLKOUT
CLKOUT
V
CC
CLK/XTAL1
V
CC
NC
GND
XTAL2
NB4N441
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin Name I/O Description
11, 12, 13, 24 V
CC
Power Supply Positive supply voltage.
3 VCC_PLL PLL Power Supply Positive supply voltage for the PLL.
1, 6, 9, 18, 19 GND Ground Ground.
20 LOCKED LVTTL Lock Output When Low, this output provides indication that the PLL is
locked and the device is in proper operating mode. When
High, the PLL is out of lock.
2, 4, 5, 10, 14 NC No Connect.
8 CLK / XTAL1,
LVTTL/LVCMOS Single Ended
Clock or XTAL Inputs
The crystal is connected between the XTAL1 and XTAL2 pin.
If driving singleended, use XTAL1 and leave XTAL2
floating.
7 XTAL2
15 SLOAD** LVTTL / LVCMOS,
Serial Load Input
Serial Load.
16 SDATA** LVTTL / LVCMOS
Serial Data Input
Serial Data Input.
17 SCLOCK** LVTTL / LVCMOS
Serial Clock Input
Serial Clock Input.
21 OE* LVTTL Input Synchronous Output Enable. When OE is HIGH or left
OPEN, the outputs are enabled. When OE is LOW, the
outputs are disabled.
22, 23 CLKOUT
CLKOUT
LVPECL Output Differential LVPECL Clock Outputs, Typically terminated with
50 W resistor to VCC – 2.0 V.
EP The Exposed Pad on the 24 pin QFN package bottom is
thermally connected to the die for improved heat transfer out
of package. The pad is not electrically connected to the die,
but is recommended to be electrically connected to GND on
the PC board.
*Pins will default HIGH when left Open
**Pins will default LOW when left Open

NB4N441MNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL MLTPRTCL PLL CLK SYN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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