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LTC4265IDE#PBF

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LTC4265
10
4265fb
For more information www.linear.com/LTC4265
applicaTions inForMaTion
In 2-event classification, a Type-2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 14.5V to
20.5V and the LTC4265 presents a class 4 load current.
The PSE then drops the input voltage into the mark voltage
range of 6.9V to 10V, signaling the 1st mark event. The PD
in the mark voltage range presents a load current between
0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Clas
-
sification and 2nd mark event occurrence. This alerts the
LTC4265
that a Type-2 PSE is present. The Type-2 PSE
then applies power to the PD and the LTC4265 charges up
the reservoir capacitor C1 with a controlled inrush current.
When C1 is fully charged, and the LTC4265 declares power
good, the T2PSE pin presents an active low signal, or low
impedance output with respect to V
IN
. The T2PSE output
becomes inactive when the LTC4265 input voltage falls
outside the normal operating range.
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE802.3at working group, Linear
notes that it is possible for a Type-2 PD to receive a
false indication of a 2-event classification if a PSE port
is pre-charged to a voltage above the detection voltage
range before the first detection cycle. The IEEE working
group modified the standard to prevent this possibility by
requiring a Type-2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
The LTC4265 conforms to this standard by internally
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
DETECTION V1
ON
UVLO
UVLO UVLOON
τ = R
LOAD
C1
TRACKS
V
IN
DETECTION V2
TIME
PD CURRENT
50
40
30
GND (V)
20
10
40mA
50
40
30
20
10
TIME
GND – V
OUT
(V)
–10
TIME
–20
–30
GND – T2PSE (V)
–40
–50
dV
dt
INRUSH
C1
=
4265 F04
INRUSH = 100mA R
CLASS
= 30.9Ω
I
LOAD
=
V
IN
R
LOAD
GND
PSE
I
IN
R
LOAD
R
CLASS
V
OUT
C1
GND
R
CLASS
T2PSE
LTC4265
V
OUT
V
IN
!
!
1st CLASS
1st MARK 2nd MARK
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
2nd CLASS
1st CLASS
2nd CLASS
LOAD, I
LOAD
INRUSH
Figure 4. V
OUT
, T2PSE, and PD Current
as a Result of 2-event Classification
LTC4265
11
4265fb
For more information www.linear.com/LTC4265
applicaTions inForMaTion
PD STABILITY DURING CLASSIFICATION
Classification presents a challenging stability problem due
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
The LTC4265 prevents this oscillation by introducing a
voltage hysteresis window between the detection and clas
-
sification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
Th
e LTC4265 also maintains a positive I-V slope throughout
the classification ranges up to the ON voltage. In the event
a PSE overshoots beyond the classification voltage range,
the available load current aids in returning the PD back
into the classification voltage range. (The PD input may
otherwise be “trapped” by a reverse-biased diode bridge
and the voltage held by the 0.1μF capacitor.)
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD, the
PSE then applies powers on the PD. When the LTC4265
input voltage rises above the ON voltage threshold, LTC4265
connects V
OUT
to V
IN
through the internal power MOSFET.
To control the power-on surge currents in the system, the
LTC4265 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
The LTC4265 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
characteristic that is independent of the PSE behavior.
Figure 5. LTC4265 Undervoltage and Overvoltage Lockout
GND
C1
5µF
MIN
V
IN
V
OUT
LTC4265
4265 F05
TO
PSE
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
CIRCUIT
PD
LOAD
CURRENT-LIMITED
TURN ON
+
INPUT LTC4265
VOLTAGE POWER MOSFET
0V TO ON* OFF
>ON* ON
<UVLO* OFF
>OVLO OFF
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD ≅ 36.1V
UVLO THRESHOLD ≅ 30.7V
OVLO THRESHOLD ≅ 71.0V
This ensures a PD using the LTC4265 interoperability
with any PSE.
UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD
operation when the input voltage is too low. In addition,
this specification allows PD designs to incorporate an
on-off hysteresis window to prevent start-up oscillations.
The LTC4265 features an ON-undervoltage lockout (UVLO)
hysteresis window (See Figure 5) that conforms with the
IEEE 802.3af/at specifications and accommodates the
voltage drop in the cable and input diode bridge at the
onset of the inrush current.
LTC4265
12
4265fb
For more information www.linear.com/LTC4265
applicaTions inForMaTion
Once C1 is fully charged, the LTC4265 turns on is internal
MOSFET and passes power to the PD load. The LTC4265
continues to power the PD load as long as the input voltage
does not fall below the UVLO threshold. When the LTC4265
input voltage falls below the UVLO threshold, the PD load
is disconnected, and classification mode resumes. C1
discharges through the LTC4265 circuitry.
COMPLEMENTARY POWERGOOD
When LTC4265 fully charges the load capacitor (C1), power
good is declared and the LTC4265 load can safely begin
operation. The LTC4265 provides complementary power
good signals that remain active during normal operation
and are de-asserted when the input voltage falls below
the UVLO threshold, when the input voltage exceeds the
over-voltage lockout (OVLO) threshold, or in the event of
a thermal shutdown. See Figure 6.
The PWRGD pin features an open collector output refer
-
enced to V
OUT
which can interface directly with the “Run”
pin of a DC/DC converter product. When power good is
declared and active, the PWRGD pin is high impedance
with respect to V
OUT
. An internal 14V clamp protects the
DC/DC converter from an excessive voltage.
The active low PWRGD pin connects to an internal, open
drain MOSFET referenced to V
IN
and can interface directly
to the shutdown pin of a DC/DC converter product. When
power good is declared and active, the PWRGD pin is low
impedance with respect to V
IN
.
Figure 6. LTC4265 Power Good Functional and State Diagram
4265 F06
BOLD LINE INDICATES HIGH CURRENT PATH
PWRGD
POWER
NOT
GOOD
INRUSH COMPLETE
ON < GND < OVLO
AND NOT IN THERMAL SHUTDOWN
GND < UVLO
GND > OVLO
OR THERMAL SHUTDOWN
POWER
GOOD
9
PWRGD
LTC4265
10
V
OUT
8
V
OUT
7
V
IN
6
V
IN
OVLO
ON
UVLO
TSD
5
CONTROL
CIRCUIT
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high imped
-
ance. This prevents the PWRGD pin that is connected to
the “Run” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
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LTC4265IDE#PBF

Mfr. #:
Buy LTC4265IDE#PBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3 at Hi Pwr PD Int Cntr w/ 2-Ev
Lifecycle:
New from this manufacturer.
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