AD7886
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REV. B
AD7886 DYNAMIC SPECIFICATIONS
The AD7886 is specified for dynamic performance specifica-
tions as well as traditional dc specifications such as integral and
differential nonlinearity. These ac specifications are required for
signal processing applications such as speech recognition, spec-
trum analysis and high speed modems. These applications require
information on the ADC’s effect on the spectral content of the
input signal. Hence, the parameters for which the AD7886 is
specified include SNR, harmonic distortion, intermodulation
distortion and peak harmonics. These terms are discussed in
more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2), excluding dc. SNR is de-
pendent upon the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to noise ratio for a sine wave
input is given by
SNR = (6.02N + 1.76) dB (1)
where N is the number of bits. Thus, for an ideal 12-bit con-
verter, SNR = 74 dB.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input, which
is sampled at a 750 kHz sampling rate. A Fast Fourier Trans-
form (FFT) plot is generated from which the SNR data can be
obtained. Figure 12 shows a typical 2048 point FFT plot with
an input signal of 100 kHz and a sampling frequency of 750 kHz.
Figure 12. AD7886 FFT Plot
The SNR obtained from this graph is 68 dB. It should be noted
that the harmonics are taken into account when calculating the
SNR.
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
obtain a measure of performance expressed in effective num-
ber of bits (N).
N =
SNR –1.76
6.02
(2)
The effective number of bits for a device can be calculated di-
rectly from its measured SNR.
Figure 13 shows a typical plot of effective number of bits versus
frequency for a sampling frequency of 750 kHz. Input frequency
range for this particular graph was limited by the test equipment
to FS/4. The effective number of bits typically falls between
10.9 and 11.2, corresponding to SNR figures of 67.38 dB and
69.18 dB.
12
11.5
11
10.5
10
0
FS/4
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
SAMPLING FREQUENCY = 750kHz
T = 25 C
A
Figure 13. Effective Number of Bits vs. Frequency
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamen-
tal. For the AD7886, THD is defined as
THD =20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
(3)
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second or-
der terms include (fa + fb) and (fa – fb) while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Using the CCIF standard, where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodu-
lation distortion is per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental, expressed in dBs. In this
case, the input consists of two, equal amplitude, low distortion
sine waves. Figure 14 shows a typical IMD plot for the AD7886.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
AD7886
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REV. B
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, the peak
will be a noise peak.
Figure 14. AD7886 IMD Plot
MICROPROCESSOR INTERFACING
The AD7886 is designed to interface to microprocessors as a
memory mapped device. Its
CS and RD control inputs are com-
mon to all memory peripheral interfacing. Figures 15 to 21
demonstrate typical interfaces for the AD7886.
AD7886–TMS320C10/TMS32020
Figures 15 and 16 show typical interfaces for the TMS320C10
and the TMS32020 DSP processors. An external timer controls
conversion start to the processor. At the end of each conversion,
the ADC’s
BUSY output interrupts the microprocessor. The
conversion result can then be read from the ADC with the fol-
lowing instruction:
IN D,ADC (ADC = ADC address)
AD788S ADSP-2100/TMS320C25/DSP56000
Some of the faster DSP processors have data access times out-
side the capabilities of the AD7886. Interfacing to such proces-
sors requires the use of either a single WAIT state or external
latches. Examples are shown in Figures 17, 18 and 19.
The use of a single WAIT state for the TMS320C25 and the
ADSP-2100 interfaces extends the read instruction to the ADC
by one processor CLK OUT cycle. In the DSP56000 example,
the ADC’s data is first clocked into 74HC374 latches before be-
ing read by the processor. The AD7886’s
CS and RD inputs are
tied permanently low, and the rising edge of
BUSY updates the
latches at the end of conversion. Both methods of overcoming
the very fast data access time required by these processors are
interchangeable, i.e., a WAIT state can be used for the DSP56000,
eliminating the need for latches or vice or versa, for the other
two interfaces.
For all three interfaces, an external timer controls conversion
start; the processor is interrupted at the end of each conversion
by the ADC’s
BUSY output. The following instruction then
reads data from the ADC:
ADSP-2100 – MR = DM(ADC)
TMS320C25 – IN D,ADC
DSP56000 – MOVEP Y:ADC,XO
Assuming the ADC is memory mapped into the top
64 locations in Y memory space. (ADC = ADC address)
PA0
PA2
D15
D0
MEN
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7886*
TMS320C10
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
EN
ADDR
ENCODE
Figure 15. AD7886-TMS320C10 Interface
A0
A15
D15
D0
IS
EN
ADDR
ENCODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7886*
TMS32020
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
Figure 16. AD7886-TMS32020 Interface
AD7886
–11–
REV. B
TIMER
DMA0
DMA13
IRQn
DMD15
DMD0
DMS
ADDRESS BUS
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7886*
ADSP-2100
*ADDITIONAL PINS OMITTED FOR CLARITY
D
Q
CLK
CLR
74HC74
DMACK
CLK
OUT
DMRD
EN
ADDR
ENCODE
5V
+
Figure 17. AD7886–ADSP-2100 Interface
ADDR
ENCODE
ADDRESS BUS
TMS320C25
CONVST
CS
AD7886*
TIMER
D15
D0
DATA BUS
DB11
DB0
INT
BUSY
RD
A0
A15
MSC
READY
IS
EN
G2
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7886–TMS320C25 Interface
EN2
ADDR
ENCODE
ADDRESS BUS
DSP56000
D23
D0
DATA BUS
CONVST
CS
DB11
DB0
AD7886*
TIMER
IRQ
RD
RD
A0
A15
DS
EN1
X/Y
BUSY
2X
74HC374
D11
D0
Q11
Q0
CLKOE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. AD7886–DSP56000 Interface
AD7886–MC68000
Applications requiring conversions to be initiated by the micro-
processor rather than an external timer may decode a
CONVST
signal from the address bus. An example is given in Figure 20
with the MC68000 processor. A write instruction starts conver-
sion while a read instruction reads the data when conversion is
complete. A delay at least as long as the ADC conversion time
must be allowed between initiating a conversion and reading the
ADC data into the processor. In Figure 20,
BUSY is used to
drive the processor into a WAIT state if the processor attempts
to read data before conversion is complete.
Conversion is initiated with a write instruction to the ADC:
Move.W D0,ADC (ADC = ADC address)
Data is transferred to the processor with a read instruction;
BUSY will force the processor to WAIT for the end of conver-
sion if a conversion is in progress.
Move.W ADC,DO (ADC = ADC address)
A0
A15
D11
D0
ADDR
ENCODE
ADDRESS BUS
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7886*
MC68000
*ADDITIONAL PINS OMITTED FOR CLARITY
R/W
EN
DTACK
AS
Figure 20. AD7886–MC68000 Interface
AD7886–Z-80/8085A
For 8-bit processors, an external latch is required to store four
bits of the conversion result (4 LSBs in Figure 21). The data is
then read in two bytes: one read from the ADC and a second
from the latch.
Figure 21 shows a typical interface suitable for the Z-80 or the
8085A. Not shown in the Figure is the 8-bit latch needed to
demultiplex the 8085A common address/data bus. The follow-
ing LOAD instruction reads the conversion result into the HL
register pair:
For the 8085A–LHLD (ADC) (ADC = ADC address)
For the Z-80–LDHL (ADC) (ADC = ADC address)
This is a two byte read instruction. The first byte to be read has
to be the high byte (DB11 to DB4). At the end of the first read
operation, the rising edge of
CS and RD clocks the 4 LSBs into
74HC374 latches. The second byte (4 LSBs) is then read from
these latches.

AD7886JP-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC LC2MOS 12-Bit 750kHz 1MHz Sampling
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