AD7886
–3–
REV. B
TIMING CHARACTERISTICS
1
(V
DD
= +5 V 6 5%, V
SS
= –5 V 6 5%, AGND = DGND = 0 V)
Limit at Limit at Limit at
T
MIN
, T
MAX
T
MIN
, T
MAX
T
MIN
, T
MAX
Parameter (J, K Versions) (B Version) (T Version) Units Conditions/Comments
t
1
50 50 50 ns min CONVST Pulse Width
1 1 1 Fs max
t
2
0 0 0 ns min CS to RD Setup Time
t
3
0 0 0 ns min CS to RD Hold Time
t
4
60 60 75 ns min RD Pulse Width
t
5
100 100 100 ns max CONVST to BUSY Propagation Delay, (C
L
= 10 pF)
t
6
57 57 70 ns max Data Access Time After RD
t
7
3
10 10 10 ns min Bus Relinquish Time After RD
50 50 60 ns max
t
8
20 20 14 ns min Data Setup Time Prior to BUSY, (C
L
= 20 pF)
10 10 0 ns min Data Setup Time Prior to
BUSY, (C
L
= 100 pF)
t
9
3
10 10 10 ns min Bus Relinquish Time After CONVST
100 100 100 ns max
t
10
0 0 0 ns min CS High to CONVST Low
t
11
0 0 0 ns min BUSY High to RD Low
t
12
250 250 250 ns typ BUSY High to CONVST Low, SHA Acquisition Time
t
13
1.333 1.333 1.333 µs min Sampling Interval
t
CONV
950 950 950 ns typ Conversion Time
1000 1000 1000 ns max
NOTES
1
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr =
tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
and t9 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the load capacitor, C
L
. This means that the times, t
7
and t
9
, quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7886 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TO OUTPUT
PIN
+2.1V
I
OH
I
OL
C
L
Figure 1. Load Circuit for Bus Access and Relinquish Time
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
VIN1, VIN2, SUM, +5REF to AGND . . . . . . –15 V to +15 V
V
REF
to AGND . . . . . . . . . . . . . . . . V
SS
–0.3 V to V
DD
+0.3 V
Digital Inputs to DGND
CS, RD, CONVST . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Digital Outputs to DGND
DB0 to DB11, BUSY . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to + 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
If V
SS
is open circuited with V
DD
and AGND applied, the V
SS
pin will be pulled
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode from V
SS
to DGND (cathode end to GND) ensures that the
AD7886
–4–
REV. B
ORDERING GUIDE
Integral
Temperature SNR Nonlinearity Package
Model
1, 2
Range (dBs) (LSBs) Option
3
AD7886JD 0°C to +70°C 65 D-28
AD7886KD 0°C to +70°C67±2.0 D-28
AD7886JP 0°C to +70°C 65 P-28A
2
AD7886KP 0°C to +70°C67±2.0 P-28A
2
AD7886BD –40°C to +85°C67 ±2.0 D-28
AD7886TD –55°C to +125°C65 ±2.0 D-28
NOTES
1Contact your sales office for availability of AD7886BD, AD7886TD and 1 MHz version.
2
Analog Devices reserves the right to ship J-Leaded Ceramic Chip Carrier (JLCCC) in lieu of PLCC packages.
3
D = Ceramic DIP; P = Plastic Leaded Chip Carrier.
PIN FUNCTION DESCRIPTION
DIP Pin
Number Mnemonic Description
Power Supply
10 & 19 V
DD
Positive Power Supply, +5 V ± 5%. Both V
DD
pins must be tied together.
15 & 24 V
SS
Negative Power Supply, –5 V ± 5%. Both V
SS
pins must be tied together.
16 & 23 AGND Analog Ground. Both AGND pins must be tied together.
5 DGND Digital Ground.
Analog and Reference Inputs
17 & 18 VIN Analog Inputs, VIN1 and VIN2. The part can be pin strapped for any one of three analog input ranges;
Range Pin Strap Signal Input
0 V to 5 V Connect VIN2 to VIN1 VIN1 & VIN2
0 V to 10 V Connect VIN2 to GND VIN1
±5 V Connect VIN2 to +5 V VIN1
20 +5REF +5 V Reference input. This input is used in conjunction with SUM and V
REF
inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
21 SUM Summing Point. This input is used in conjunction with +5REF and V
REF
inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
22 V
REF
Voltage Reference Input. The AD7886 is specified with V
REF
= –3.5 V.
Interface and Control
1–4, DB7–DB4 Three-state data outputs.
6–9, DB3–DB0 These outputs are controlled by
CS and RD. DB11 is the Most Significant Bit (MSB).
25–28 DB11–DB8
11
BUSY BUSY Output indicates converter status. BUSY is low during conversion.
12
CS Chip Select Input. The device is selected when this input is low.
13
RD Read Input. This active low signal, in conjunction with CS, is used to enable the output data three-state
drivers.
14 CONVST Conversion Start Input. This input is used to start conversion.
AD7886
–5–
REV. B
PIN CONFIGURATIONS
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
(Not to Scale)
AD7886
DB7
DB6
DB5
DB4
DGND
DB3
DB2
DB1
DB0
V
DD
DB8
DB9
DB10
DB11
V
SS
AGND
V
REF
SUM
+5REF
V
DD
VIN2
VIN1
AGND
V
SS
CS
RD
CONVST
BUSY
TERMINOLOGY
Unipolar Offset Error
The ideal first code transition should occur when the analog
input is 1 LSB above AGND. The deviation of the actual transi-
tion from that point is termed the offset error.
Bipolar Zero Error
The ideal midscale transition (i.e., 0111 1111 1111 to 1000
0000 0000) for the +5 V range should occur when the analog
input is at zero volts. Bipolar zero error is the deviation of the
actual transition from that point.
Gain Error
In the unipolar mode, gain error is measured with respect to the
first and last code transition points. The ideal difference be-
tween these points is FS–2 LSBs. For bipolar applications, the
gain error is measured from the midscale transition to both the
first and last code transitions. The ideal difference in this case is
FS/2–1 LSB. The gain error is defined as the deviation between
the ideal difference, given above, and the measured difference.
For the bipolar case, there are two gain errors; the figure in the
specification page represents the worst case. Ideal FS depends
on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF
and for the 0 V to 10 V and +5 V ranges, ideal FS = 2 × + 5REF.
CONVERTER DETAILS
The AD7886 is a triple-pass flash ADC that uses 15 compara-
tors in a 4-bit flash technique to perform the 12-bit conversion
procedure. Each of the 4096 quantization levels is realized inter-
nally with a precision resistor DAC.
The fifteen comparators first compare the analog input voltage
to the V
REF
/16 voltages of the resistor array. This determines the
four most significant bits and selects 1 out of 16 voltage seg-
ments. The comparators are then switched to 15 subvoltages on
that segment to determine the next four bits and select 1 out of
256 voltage segments. A further switching of the comparators to
another 15 subvoltages produces the complete 12-bit conversion
result. The 12 bits of data are then stored internally in a three-
state output latch.
REFERENCE INPUT
The AD7886 operates from a 3.5 V reference, which must be
provided at the V
REF
input. Two on-chip resistors for use with
an external amplifier can be used for deriving 3.5 V from stan-
dard 5 V references. Figure 2 shows an example with the AD586
which a is a high performance voltage reference exhibiting
excellent stability performance, 5 ppm/°C max. The external
amplifier serves a second function of force/sensing the V
REF
input. Force/sensing minimizes error contributions from
AD7886*
SUM
+5REF
TO DAC
+
AD586
V
OUT
+V
IN
GND
AGND
+V
+5V
R1
9k
R2
6.3k
C1
10µF
C2
0.1µF
AD707
V
REF
–3.5V
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Typical Reference Circuitry
PLCC
AGND
VIN1
VIN2
DB4
DB5
DB6
DB11
DB10
DB9
DB8
DB7
AGND
SUM
+5REF
DB2
DB1
DB0
DGND
DB3
V
SS
V
REF
V
DD
CS
RD
CONVST
V
SS
V
DD
BUSY
AD7886
TOP VIEW
(Not to Scale)
5
6
7
8
9
10
11
28 27 2612
3
4
25
24
23
22
21
20
19
12
13 14 15 16 17 18

AD7886JP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC LC2MOS 12-Bit 750kHz 1MHz Sampling
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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