AD8310
Rev. F | Page 3 of 24
SPECIFICATIONS
T
A
= 25°C, V
S
= 5 V, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT STAGE Inputs INHI, INLO
Maximum Input
1
Single-ended, p-p ±2.0 ±2.2 V
4 dBV
Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBm
Differential drive, p-p 20 dBm
Noise Floor Terminated 50 Ω source 1.28 nV/√Hz
Equivalent Power in 50 Ω 440 MHz bandwidth −78 dBm
Input Resistance From INHI to INLO 800 1000 1200 Ω
Input Capacitance From INHI to INLO 1.4 pF
DC Bias Voltage Either input 3.2 V
LOGARITHMIC AMPLIFIER Output VOUT
±3 dB Error Dynamic Range From noise floor to maximum input 95 dB
Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dB
Overtemperature, −40°C < T
A
< +85°C 20 26 mV/dB
Intercept (Log Offset)
2
10 MHz ≤ f ≤ 200 MHz −115 −108 −99 dBV
Equivalent dBm (re 50 Ω) −102 −95 −86 dBm
Overtemperature, −40°C ≤ T
A
≤ +85°C −120 −96 dBV
Equivalent dBm (re 50 Ω) −107 −83 dBm
Temperature sensitivity −0.04 dB/°C
Linearity Error (Ripple) Input from −88 dBV (−75 dBm) to +2 dBV (+15 dBm) ±0.4 dB
Output Voltage Input = −91 dBV (−78 dBm) 0.4 V
Input = 9 dBV (22 dBm) 2.6 V
Minimum Load Resistance, R
L
100 Ω
Maximum Sink Current 0.5 mA
Output Resistance 0.05 Ω
Video Bandwidth 25 MHz
Rise Time (10% to 90%) Input level = −43 dBV (−30 dBm), R
L
≥ 402 Ω, C
L
≤ 68 pF 15 ns
Input level = −3 dBV (+10 dBm), R
L
≥ 402 Ω, C
L
≤ 68 pF 20 ns
Fall Time (90% to 10%) Input level = −43 dBV (−30 dBm), R
L
≥ 402 Ω, C
L
≤ 68 pF 30 ns
Input level = −3 dBV (+10 dBm), R
L
≥ 402 Ω, C
L
≤ 68 pF 40 ns
Output Settling Time to 1% Input level = −13 dBV (0 dBm), R
L
≥ 402 Ω, C
L
≤ 68 pF 40 ns
POWER INTERFACES
Supply Voltage, VPOS 2.7 5.5 V
Quiescent Current Zero signal 6.5 8.0 9.5 mA
Overtemperature −40°C < T
A
< +85°C 5.5 8.5 10 mA
Disable Current 0.05 μA
Logic Level to Enable Power High condition, −40°C < T
A
< +85°C 2.3 V
Input Current When High 3 V at ENBL 35 μA
Logic Level to Disable Power Low condition, −40°C < T
A
< +85°C 0.8 V
1
The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed
offset of 13 dBm in the special case of a 50 Ω termination.
2
Guaranteed but not tested; limits are specified at six sigma levels.
AD8310
Rev. F | Page 4 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, V
S
7.5 V
Input Power (re 50 Ω), Single-Ended 18 dBm
Differential Drive 22 dBm
Internal Power Dissipation 200 mW
θ
JA
200°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8310
Rev. F | Page 5 of 24
01084-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO
1
INHI
8
COMM
2
ENBL
7
OFLT
3
BFIN
6
VPOS
5
AD8310
TOP VIEW
(Not to Scale)
VOUT
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.
2 COMM Common Pin. Usually grounded.
3 OFLT Offset Filter Access. Nominally at about 1.75 V.
4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load.
5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6 BFIN Buffer Input. Used to lower postdetection bandwidth.
7 ENBL CMOS Compatible Chip Enable. Active when high.
8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2.

AD8310ARM-REEL7

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Logarithmic Amplifiers V-Out DC to 440 MHz 95dB
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