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74LVT373PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15
74LVT373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 21 November 2011 7 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
[1] Typical values are measured at T
amb
=25C and V
CC
= 3.3 V and 2.7 V respectively.
[2] t
su
is the same as t
su(L)
and t
su(H)
.
[3] t
h
is the same as t
h(L)
and t
h(H)
.
[4] t
W
is the same as t
WL
and t
WH
.
t
PHZ
HIGH to OFF-state
propagation delay
OE to Qn; see Figure 7
V
CC
= 3.0 V to 3.6 V 1.8 3.2 5.1 ns
V
CC
= 2.7 V 1.9 3.5 5.3 ns
t
PLZ
LOW to OFF-state
propagation delay
OE to Qn; see Figure 8
V
CC
= 3.0 V to 3.6 V 2.1 3.2 4.6 ns
V
CC
= 2.7 V 2.0 3.0 4.6 ns
t
su
set-up time Dn to LE; see Figure 9
[2]
V
CC
= 3.0 V to 3.6 V 1.1 - - ns
V
CC
= 2.7 V 1.0 - - ns
t
h
hold time Dn to LE; see Figure 9
[3]
V
CC
= 3.0 V to 3.6 V 1.4 - - ns
V
CC
= 2.7 V 1.4 - - ns
t
W
pulse width LE input HIGH; see Figure 5
[4]
V
CC
= 3.0 V to 3.6 V 3.0 - - ns
V
CC
= 2.7 V 3.0 - - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions T
amb
= 40 C to +85 C Unit
Min Typ
[1]
Max
74LVT373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 21 November 2011 8 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
11. Waveforms
Measurement points are given in Table 8. Measurement points are given in Table 8.
Fig 5. Propagation delays latch enable input (LE) to
output (Qn), and latch enable (LE) pulse width
Fig 6. Propagation delay data input (Dn) to
output (Qn)
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur
with the output load.
Measurement points are given in Table 8
.
Fig 7. Output enable time to HIGH-state and output
disable time from HIGH-state
Fig 8. Output enable time to LOW-state and output
disable time from LOW-state
Measurement points are given in Table 8.
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data setup and hold times for data (Dn) and latch enable (LE) inputs
001aai743
LE
input
Qn
output
t
PHL
t
PLH
t
WH
V
M
V
OH
V
I
0 V
V
OL
V
M
t
WL
001aai742
Dn input
Qn output
t
PHL
t
PLH
0 V
V
I
V
M
V
M
V
OH
V
OL
001aai744
t
h(L)
t
su(L)
t
h(H)
t
su(H)
V
M
V
M
V
I
0 V
V
I
0 V
LE input
Dn input
Table 8. Measurement points
Input Output
V
M
V
M
V
X
V
Y
1.5V 1.5V V
OL
+ 0.3 V V
OH
0.3 V
74LVT373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 21 November 2011 9 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
Test data is given in Table 9.
Definitions test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= Test voltage for switching times.
Fig 10. Test circuit for measuring switching times
V
EXT
V
CC
V
I
V
O
001aae235
DUT
C
L
R
T
R
L
R
L
PULSE
GENERATOR
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
Table 9. Test data
Input Load V
EXT
V
I
f
i
t
W
t
r
, t
f
C
L
R
L
t
PHZ
, t
PZH
t
PLZ
, t
PZL
t
PLH
, t
PHL
2.7 V 10 MHz 500 ns 2.5 ns 50 pF 500 GND 6 V open
P1-P3P4-P6P7-P9P10-P12P13-P15

74LVT373PW,118

Mfr. #:
Buy 74LVT373PW,118
Manufacturer:
NXP Semiconductors
Description:
IC TRANSP LATCH OCT 3-ST 20TSSOP
Lifecycle:
New from this manufacturer.
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