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MC100LVEL40DWG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1 Publication Order Number:
MC100LVEL40/D
MC100LVEL40
3.3/5VECL Differential
Phase−Frequency Detector
Description
The MC100LVEL40 is a three state phase frequency−detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V power supply.
When the reference (R) and the feedback (FB) inputs are unequal in
frequency and/or phase the differential up (U) and down (D) outputs
will provide pulse streams which when subtracted and integrated
provide an error voltage for control of a VCO.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
For application information, refer to AND8040/D, “Phase Lock
Loop Operation.”
The 100 Series Contains Temperature Compensation
Features
• 250 MHz Typical Bandwidth
• PECL Mode Operating Range:
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Internal Input Pulldown Resistor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM
SO−20
DW SUFFIX
CASE 751D
1
20
http://onsemi.com
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
20
1
100LVEL40
AWLYYWWG
MC100LVEL40
http://onsemi.com
2
Figure 1. 20−Lead Pinout (Top View)
1920 18 17 16 15 14
21 34567
NC
13
8
12
9
11
10
V
CCO
UUV
EE
DDV
CCO
NC NC
NC NC R R V
BB
FB FB V
CC
NC NC
Figure 2. Logic Diagram
PIN FUNCTION
U, U
ECL Up Differential Outputs
D,
D ECL Down Differential Outputs
FB, FB ECL Feedback Differential Inputs
R, R ECL Reference Differential Inputs
V
BB
Reference Voltage Output
V
CC
, V
CCO
Positive Supply
V
EE
Negative Supply
NC No Connect
Table 1. PIN DESCRIPTION
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
R
V
BB
FB
FB
SQ
R
SQ
R
RU
U
D
D
V
EE
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model > 2 kV
Moisture Sensitivity (Note 1) Pb Pkg Pb−Free Pkg
SOIC−20 Level 1 Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 356 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100LVEL40
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6 to 0
−6 to 0
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
306
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W
T
sol
Wave Solder Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. LVPECL DC CHARACTERISTICS V
CC
= 3.3 V, V
EE
= 0 V (Note 2)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 38 45 38 47 38 47 mA
V
OH
Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1380 1490 1595 1680 mV
V
IH
Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV
V
BB
Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 7)
Vpp < 500 mV
Vpp y 500 mV
1.3
1.5
3.3
3.3
1.2
1.4
3.3
3.3
1.2
1.4
3.3
3.3
V
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current Others
R, FB
0.5
−300
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
3. Outputs are terminated through a 50 W resistor to V
CC
− 2 V.
4. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and
1 V.
P1-P3P4-P6

MC100LVEL40DWG

Mfr. #:
Buy MC100LVEL40DWG
Manufacturer:
ON Semiconductor
Description:
Phase Detectors / Shifters 3.3V/5V ECL Diff Phase Freq. Detector
Lifecycle:
New from this manufacturer.
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