7 of 29 June 18, 2014
IDT 89HPES8T5A Data Sheet
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES8T5A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
SWMODE[2:0] I Switch Mode. These configuration pins determine the PES8T5A switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
WAKEN I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through the WAKEDIR bit setting
in the WAKEUPCNTL register.
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal Type Name/Description
V
DD
CORE I Core VDD. Power supply for core logic.
V
DD
IO I I/O VDD. LVTTL I/O buffer power supply.
V
DD
PE I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
V
DD
APE I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
V
TT
PE I PCI Express Termination Power.
V
SS
I Ground.
Table 7 Power and Ground Pins
Signal Type Name/Description
Table 5 System Pins (Part 2 of 2)
