Philips Semiconductors Product specification
SA607Low voltage high performance mixer FM IF system
1997 Nov 07
5
CIRCUIT DESCRIPTION
The SA607 is an IF signal processing system suitable for second IF
systems with input frequency as high as 150MHz. The bandwidth of
the IF amplifier and limiter is at least 2MHz with 90dB of gain. The
gain/bandwidth distribution is optimized for 455kHz, 1.5kΩ source
applications. The overall system is well-suited to battery operation
as well as high performance and high quality products of all types.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer
characteristics include a noise figure of 6.2dB, conversion gain of
17dB, and input third-order intercept of –9dBm. The oscillator will
operate in excess of 200MHz in L/C tank configurations. Hartley or
Colpitts circuits can be used up to 100MHz for xtal configurations.
Butler oscillators are recommended for xtal configurations up to
150MHz.
The output impedance of the mixer is a 1.5kΩ resistor permitting
direct connection to a 455kHz ceramic filter. The input resistance of
the limiting IF amplifiers is also 1.5kΩ. With most 455kHz ceramic
filters and many crystal filters, no impedance matching network is
necessary. The IF amplifier has 43dB of gain and 5.5MHz
bandwidth. The IF limiter has 60dB of gain and 4.5MHz bandwidth.
To achieve optimum linearity of the log signal strength indicator,
there must be a 12dB(v) insertion loss between the first and second
IF stages. If the IF filter or interstage network does not cause
12dB(v) insertion loss, a fixed or variable resistor or an L pad for
simultaneous loss and impedance matching can be added between
the first IF output (Pin 16) and the interstage network. The overall
gain will then be 90dB with 2MHz bandwidth.
The signal from the second limiting amplifier goes to a Gilbert cell
quadrature detector. One port of the Gilbert cell is internally driven
by the IF. The other output of the IF is AC-coupled to a tuned
quadrature network. This signal, which now has a 90
° phase
relationship to the internal signal, drives the other port of the
multiplier cell.
The demodulated output of the quadrature drives an internal op
amp. This op amp can be configured as a unity gain buffer, or for
simultaneous gain, filtering, and 2nd-order temperature
compensation if needed. It can drive an AC load as low as 5kΩ with
a rail-to-rail output.
A log signal strength completes the circuitry. The output range is
greater than 90dB and is temperature compensated. This log signal
strength indicator exceeds the criteria for AMPs or TACs cellular
telephone. This signal is buffered through an internal unity gain op
amp. The frequency check pin provides a buffered limiter output.
This is useful for implementing an AFC (Automatic Frequency
Check) function. This same output can also be used in conjunction
with limiter output (Pin 11) for demodulating FSK (Frequency Shift
Keying) data. Both pins are of the same amplitude, but 180° out of
phase.
NOTE: Limiter output or Frequency Check output has drive
capability of a load minimum of 2kΩ or higher to obtain 115mV
output level.
NOTE: dB(v) = 20log V
OUT
/V
IN
